Hans Summers wrote:

Hello

I have built 2 very simple 2-chip frequency counters with 8 LED binary
readout see http://www.hanssummers.com/radio/sfreq/index.htm . My Mk2
counter is extremely small (just 25 x 16 x 16mm) and consumes a low current
of 5mA max.

The question relates to the 4.096MHz oscillator which uses the internal
oscillator of the 74HC4060. Of the 5mA current consumption, 1.2mA is used by
the LED's when max 7 are on at any one time. About 0.8mA by the
diode-resistor gate logic, transistor switch, 74HC4040 and the voltage
regulator. Fully 3mA is wasted on the 74HC4060 crystal oscillator + divider.
It seems wrong to spend 60% of your current consumption on an oscillator,
compared to less than 25% on the LED's.

In the pursuit of excellence in this design, I would like to cut the current
consumption of the oscillator section. Does anyone know of a better
arrangement that will cut current consumption? Increasing the series
resistor wasn't the solution. I put a 100K variable in here in place of the
original 2K2. Initially as the resistor was increased the current
consumption fell, but at higher resistances the current consumption
increased quite dramatically. The optimum was at close to 4K7.

73 Hans G0UPL
http://www.HansSummers.com




Here's a suggestion. I've never tried this, so YMMV. You're using a
circuit that looks like:

|\ ___
.---| O-----|___|--.
| |/ R1 |
| |
| ___ |
o------|___|--------o
| R2 |
| _ |
| | | |
o-------|| ||-------o
| |_| |
| 4.096MHz |
--- C2 --- C1
--- ---
| |
| |
=== ===
GND GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

Yes?

And you've maximized R2 and dinked with the value of R1, and the best
you can get is R1 = 4.7kOhm?

Probably what is happening is that you're fighting two contradictory
effects in the circuit: Effect one is that the inverter wants to have a
low-impedance output, so a low value of R1 will pull a lot of current
from the inverter output. Effect two is that a CMOS inverter is
designed assuming that it will be turned on hard; if it isn't then the
complementary pair of FETs just conduct current from the VSS rail to VDD.

I think that when you adjust R1 higher you're loading the output less,
but you're also supplying less voltage to the input. Your 4.7kOhm value
saves you output current, but drops the input voltage enough so that you
start seeing more input current.

Why don't you try playing with your feedback a little bit? I'm assuming
that you have C1 = C2. If you decrease C2 while increasing C1 so that
the series combination of C2 and C1 stays the same the voltage at the
inverter input should be stepped up. Depending on about a gazillion
factors this may reduce your current consumption.

I would try the circuit below:


|\ ___
.---| O-----|___|--.
| |/ R1 |
| |
| ___ |
o------|___|--------o
| R2 |
| _ |
| | | |
o-------|| ||-------o
| |_| |
| 4.096MHz |
--- C2 --- C1
--- ---
| |
o--------o Vtest |
| ===
--- C3 GND
---
|
|
===
GND
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

Make sure R2 is as large as you can get away with and make C3 about ten
times bigger than the crystal's load capacitance, and leave C2 at about
the crystal's load capacitance. Now measure the voltage at Vtest
(please have an O-Scope!). Because you know C2 and C3 you can calculate
the voltage at the inverter input and keep it to 5Vp-p as you play with
C1 and R1.

Now play with C1 and R1 and see if you can (a) reduce power even more,
(b) keep a good strong signal at the inverter input and (c) keep your
desired frequency stability. Increasing C1 should give you more voltage
at C2, increasing R1 should give you less. There should be a point
where you get good performance at less current than you're getting now.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com