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Error in textbook?
Hi all,
In his very skimpy explanation on basic DC biasing for FETs, Chris Bowick (in RF Circuit Design) gives the suggested bias network that I've posted to a.b.s.e under the same subject title as this message. I don't see how this arrangement can possibly work for any N-Jfet since for one thing at least, the gate is positive with respect to the source. I've tried to scan the page in and post that, but the scanner's messing about, so I've redrawn it as a spice schematic and posted that instead. If it turns out the arrangement is incorrect, as I suspect, I will endeavor to post his explanation for how he arrived at these resistor values. So: is he wrong or am I nuts? p. Note: for anyone using LTspice, the fet shown is not a working model; I'm simply posting this as a diagram for illustration. -- "What is now proved was once only imagin'd." - William Blake, 1793. |
On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge
wrote: Hi all, In his very skimpy explanation on basic DC biasing for FETs, Chris Bowick (in RF Circuit Design) gives the suggested bias network that I've posted to a.b.s.e under the same subject title as this message. I don't see how this arrangement can possibly work for any N-Jfet since for one thing at least, the gate is positive with respect to the source. I've tried to scan the page in and post that, but the scanner's messing about, so I've redrawn it as a spice schematic and posted that instead. If it turns out the arrangement is incorrect, as I suspect, I will endeavor to post his explanation for how he arrived at these resistor values. So: is he wrong or am I nuts? p. Note: for anyone using LTspice, the fet shown is not a working model; I'm simply posting this as a diagram for illustration. Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. The next example on the same page illustrates that Vg must be near zero, not +5. Really silly, putting these two circuits side-by-side. John |
On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge
wrote: Hi all, In his very skimpy explanation on basic DC biasing for FETs, Chris Bowick (in RF Circuit Design) gives the suggested bias network that I've posted to a.b.s.e under the same subject title as this message. I don't see how this arrangement can possibly work for any N-Jfet since for one thing at least, the gate is positive with respect to the source. I've tried to scan the page in and post that, but the scanner's messing about, so I've redrawn it as a spice schematic and posted that instead. If it turns out the arrangement is incorrect, as I suspect, I will endeavor to post his explanation for how he arrived at these resistor values. So: is he wrong or am I nuts? p. Note: for anyone using LTspice, the fet shown is not a working model; I'm simply posting this as a diagram for illustration. Oh, the skin depth equation on p 10 is apparently wrong, too. John |
On Wed, 11 Aug 2004 13:01:51 -0700, John Larkin
wrote: Oh, the skin depth equation on p 10 is apparently wrong, too. Excellent, John. Many thanks. It's reassuring you've seen the actual book for yourself, but it would have been better if you'd have hung fire until Active8 or someone else impulsive jumped in and accused me of getting it all wrong. There are quite a few stoopid errors in this otherwise excellent book. This one was just a bit more obvious than the others. :-) Thanks again for the prompt response. -- "What is now proved was once only imagin'd." - William Blake, 1793. |
Hi Paul,
Seems like it was meant for a MOSFET or someone typeset a wrong resistor value and then all this got lost in the review process. Probably best to let the author know so he can correct in the next ed. What is now proved was once only imagin'd." - William Blake, 1793. I like this one! It reminds me of a mechanical engineering book I got from my late father in law, a book he received from someone even more senior. Under radio frequency waves it states that this is a wonderous and strange phenomenon that is yet to be explaineth. And here I am an RF guy... Regards, Joerg http://www.analogconsultants.com |
"Paul Burridge" wrote in message ... Hi all, In his very skimpy explanation on basic DC biasing for FETs, Chris Bowick (in RF Circuit Design) gives the suggested bias network that I've posted to a.b.s.e under the same subject title as this message. I don't see how this arrangement can possibly work for any N-Jfet since for one thing at least, the gate is positive with respect to the source. I've tried to scan the page in and post that, but the scanner's messing about, so I've redrawn it as a spice schematic and posted that instead. If it turns out the arrangement is incorrect, as I suspect, I will endeavor to post his explanation for how he arrived at these resistor values. So: is he wrong or am I nuts? Have a look on the inside flap to see if he's a reader in engineering at some University. If so, then they probably are errors. p. Note: for anyone using LTspice, the fet shown is not a working model; I'm simply posting this as a diagram for illustration. -- "What is now proved was once only imagin'd." - William Blake, 1793. |
John Larkin wrote: Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. The next example on the same page illustrates that Vg must be near zero, not +5. Really silly, putting these two circuits side-by-side. John Shhhh...don't tell the resident idiot, but it's going to be damn tough biasing that IDSS=5mA JFET to a quiescent ID=10ma.... |
On Thu, 12 Aug 2004 02:58:57 GMT, Fred Bloggs
wrote: John Larkin wrote: Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. The next example on the same page illustrates that Vg must be near zero, not +5. Really silly, putting these two circuits side-by-side. John Shhhh...don't tell the resident idiot, but it's going to be damn tough biasing that IDSS=5mA JFET to a quiescent ID=10ma.... Good point. Bowick seems to be applying the jfet gate-voltage equation backwards to enhance it! The other example on page 120 is even sillier. Just shows you that an RF expert can't always handle DC. John |
On Wed, 11 Aug 2004 21:19:04 +0100, Paul Burridge wrote:
On Wed, 11 Aug 2004 13:01:51 -0700, John Larkin wrote: Oh, the skin depth equation on p 10 is apparently wrong, too. Excellent, John. Many thanks. It's reassuring you've seen the actual book for yourself, but it would have been better if you'd have hung fire until Active8 or someone else impulsive jumped in and accused me of getting it all wrong. There are quite a few stoopid errors in this otherwise excellent book. This one was just a bit more obvious than the others. :-) Thanks again for the prompt response. Hey POS troll. How would you see it if I'm kill filed? -- No Regards, Mike |
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On Wed, 11 Aug 2004 12:59:22 -0700, John Larkin wrote:
On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge wrote: Hi all, In his very skimpy explanation on basic DC biasing for FETs, Chris Bowick (in RF Circuit Design) gives the suggested bias network that I've posted to a.b.s.e under the same subject title as this message. I don't see how this arrangement can possibly work for any N-Jfet since for one thing at least, the gate is positive with respect to the source. I've tried to scan the page in and post that, but the scanner's messing about, so I've redrawn it as a spice schematic and posted that instead. If it turns out the arrangement is incorrect, as I suspect, I will endeavor to post his explanation for how he arrived at these resistor values. So: is he wrong or am I nuts? p. Note: for anyone using LTspice, the fet shown is not a working model; I'm simply posting this as a diagram for illustration. Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. Well, when you rearrange the Id eq to get Vgs, you get [ ] | | | ( ) | | | I | | | | D | | V = -Vp| sqrt| ------- | - 1 | GS | | I | | | | DSS | | | ( ) | | | [ ] You can swap the terms inside the brackets by moving the negative sign of Vp inside, which gives you Bowick's version. Either way, you get the wrong answer unless you recall that sqrt(4) = +/- 2 So you have to apply some reasoning. Thus (3 dots in a triangle) Burridge = idiot^100. QED The next example on the same page illustrates that Vg must be near zero, not +5. Really silly, putting these two circuits side-by-side. John -- Best Regards, Mike |
On Thu, 12 Aug 2004 08:28:41 -0700, John Larkin wrote:
On Thu, 12 Aug 2004 02:58:57 GMT, Fred Bloggs wrote: John Larkin wrote: Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. The next example on the same page illustrates that Vg must be near zero, not +5. Really silly, putting these two circuits side-by-side. John Shhhh...don't tell the resident idiot, but it's going to be damn tough biasing that IDSS=5mA JFET to a quiescent ID=10ma.... LOL. That was an astute observation, not that I'm surprised. Either I didn't read that part of the book ( I have a NOV '82 Siliconix data book that sufficed) or I blew it off. Good point. Bowick seems to be applying the jfet gate-voltage equation backwards to enhance it! The other example on page 120 is even sillier. I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small values of 2.48, yup. I better compare all his refs to my own collection of app notes in der future and check the math. Just shows you that an RF expert can't always handle DC. It's his math, actually. See my other post and while you're at it, reply to my reply to the idiot so he can see it. A blank post will suffice -) -- Best Regards, Mike |
On Thu, 12 Aug 2004 18:54:55 -0400, Active8 wrote:
On Wed, 11 Aug 2004 12:59:22 -0700, John Larkin wrote: On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge wrote: Hi all, In his very skimpy explanation on basic DC biasing for FETs, Chris Bowick (in RF Circuit Design) gives the suggested bias network that I've posted to a.b.s.e under the same subject title as this message. I don't see how this arrangement can possibly work for any N-Jfet since for one thing at least, the gate is positive with respect to the source. I've tried to scan the page in and post that, but the scanner's messing about, so I've redrawn it as a spice schematic and posted that instead. If it turns out the arrangement is incorrect, as I suspect, I will endeavor to post his explanation for how he arrived at these resistor values. So: is he wrong or am I nuts? p. Note: for anyone using LTspice, the fet shown is not a working model; I'm simply posting this as a diagram for illustration. Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. Well, when you rearrange the Id eq to get Vgs, you get [ ] | | | ( ) | | | I | | | | D | | V = -Vp| sqrt| ------- | - 1 | GS | | I | | | | DSS | | | ( ) | | | [ ] You can swap the terms inside the brackets by moving the negative sign of Vp inside, which gives you Bowick's version. Either way, you get the wrong answer unless you recall that sqrt(4) = +/- 2 So you have to apply some reasoning. Strike that. I'd didn't work. Gots me wondering WTF now. |
On Thu, 12 Aug 2004 19:12:04 -0400, Active8 wrote:
snip So you have to apply some reasoning. Strike that. I'd didn't work. Gots me wondering WTF now. . . . Burridge = idiot^100. ^^^^^^^^^^^^^^^^^^^^ That still works for all values of idiot 1. QED Otay. You write the node eq for Vgs, expand Shockley's eq., equate the two, rearrange, solve the quadratic and pick the correct root. Sorry I thrashed around on that. -- Best Regards, Mike |
On Thu, 12 Aug 2004 18:57:34 -0400, Active8
wrote: I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small values of 2.48, yup. Now *that's* funny! Too bad Paul won't see it! John |
On Thu, 12 Aug 2004 16:47:30 -0700, John Larkin wrote:
On Thu, 12 Aug 2004 18:57:34 -0400, Active8 wrote: I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small values of 2.48, yup. Now *that's* funny! Too bad Paul won't see it! John Based on some recent posts, I suspect that duplicitous white trash POS is reading my posts despite his blasting JT for "not sticking to his [ctrl-k] guns" just to see what I'm saying behind his back. It's not really backstabbing since it's out in the open and I'd say it to his face before I rearrange it like so much algebra. I think he needs a good old fashioned hillbilly ass-whoopin' what with the way he's flaming a few of us and making hillbilly slurs. Apologies again for the multiple replies to self while working this out. That Siliconix book used design curves and iterative stuff. I'd be impressed if SFB Burridge (rhymes with porridge - like the space between his audio sensors) could solve the bias net (or any net) on his own. -- Best Regards, Mike |
In article ,
Fred Bloggs wrote: John Larkin wrote: Looks like the jfet will be saturated with the values shown, not good for RF work. Looks like he got the sign of Vgs backwards. The next example on the same page illustrates that Vg must be near zero, not +5. Really silly, putting these two circuits side-by-side. John Shhhh...don't tell the resident idiot, but it's going to be damn tough biasing that IDSS=5mA JFET to a quiescent ID=10ma.... Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just apply a positive bias to the gate. I've had as much as 2 or 3 A flow through a JFET this way. -- -- forging knowledge |
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Paul Burridge wrote: On Fri, 13 Aug 2004 03:49:15 +0000 (UTC), (Ken Smith) wrote: Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just apply a positive bias to the gate. I've had as much as 2 or 3 A flow through a JFET this way. How many mS did the Fet last? I suppose you could always stand there with a can of arctic spray directed on it, but I doubt the customer would be impressed. ;-) Actually there have been systems produced that did run quite hot and were arranged with a liquid nitrogen drip onto the electronics to keep things cool. |
In (rec.radio.amateur.homebrew), Fred Bloggs wrote:
Paul Burridge wrote: On Fri, 13 Aug 2004 03:49:15 +0000 (UTC), (Ken Smith) wrote: Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just apply a positive bias to the gate. I've had as much as 2 or 3 A flow through a JFET this way. How many mS did the Fet last? I suppose you could always stand there with a can of arctic spray directed on it, but I doubt the customer would be impressed. ;-) Actually there have been systems produced that did run quite hot and were arranged with a liquid nitrogen drip onto the electronics to keep things cool. One model of Seymour Cray's computers ran with the logic immersed in a bath of chilled Fluorinert or some such, with a fairly hefty pump to keep the coolant recirculating through the chiller. -- Paul Raj Khangure mumbled: Every time someone calls Java a programming language a fairy dies? From frustration, if nothing else. DaZZa, in a.t-s.r |
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On Fri, 13 Aug 2004 12:54:14 +0000, Mike Andrews wrote:
In (rec.radio.amateur.homebrew), Fred Bloggs wrote: Paul Burridge wrote: On Fri, 13 Aug 2004 03:49:15 +0000 (UTC), (Ken Smith) wrote: Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just apply a positive bias to the gate. I've had as much as 2 or 3 A flow through a JFET this way. How many mS did the Fet last? I suppose you could always stand there with a can of arctic spray directed on it, but I doubt the customer would be impressed. ;-) Actually there have been systems produced that did run quite hot and were arranged with a liquid nitrogen drip onto the electronics to keep things cool. One model of Seymour Cray's computers ran with the logic immersed in a bath of chilled Fluorinert or some such, with a fairly hefty pump to keep the coolant recirculating through the chiller. Many years before, IBM was going to use a CFC (FC86, IIRC) in much the same way. The logic modules were about 4" cubes with a multi-layer (50-60, can't remember) ceramic substrate with 100 logic chips on one side, a water-filled cold-plate on the other, and filled with the CFC. Heat was removed from back-side of the chips by boiling the CFC. I worked on a logic tester in '75 that immersed the un-encapsulated substrate into a bath of CFCs so it could be probed. Unfortunately, boiling the CFC also distilled it, leaving any contamination on the chips. The result came to be known as the "black plague". Because of the "black plague" the "LEM" (Liquid Encapsulated Module) was replaced by a similar looking (though shorter) "TCM" (Thermal Conduction Module) which used pistons on the backside of the chips (increased to 121 chips) to transfer heat (10W per chip, 1200W total) to the cold-plate and filled with helium. The TCMs were used throught the '80s and early '90s for the high-end ECL systems. -- Keith |
I read in sci.electronics.design that Keith wrote (in
) about 'Error in textbook?', on Sat, 14 Aug 2004: Unfortunately, boiling the CFC also distilled it, leaving any contamination on the chips. Sulfur hexafluoride might have been better, but it's probably more costly than CFCs were. -- Regards, John Woodgate, OOO - Own Opinions Only. The good news is that nothing is compulsory. The bad news is that everything is prohibited. http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk |
In (rec.radio.amateur.homebrew), Keith wrote:
Unfortunately, boiling the CFC also distilled it, leaving any contamination on the chips. The result came to be known as the "black plague". Because of the "black plague" the "LEM" (Liquid Encapsulated Module) was replaced by a similar looking (though shorter) "TCM" (Thermal Conduction Module) which used pistons on the backside of the chips (increased to 121 chips) to transfer heat (10W per chip, 1200W total) to the cold-plate and filled with helium. The TCMs were used throught the '80s and early '90s for the high-end ECL systems. Yep. I've got a TCM somewhere at home; I need to take a pic of it for my web page. IIRC, it has 1024 pins, and the largest ZIF socket I've ever seen. The cold plate on the TCM is about 4.5" square, very smooth, and designed to go on a larger water-cooled manifold with some dozens more TCMs, all getting water from a chiller. They're called "wet-frame" machines by a lot of us who dealt with them, and especially by those of us who had a leak develop somewhere in the cooling system. Nowadays one TCM's circuitry fits on a single chip, at a meager fraction of the TCM's dissipation, and is enormously faster, so that (for 9672 hardware, anyway) IBM ships the machine with a bunch of CPUs and licenses you the code to turn on as many as you're paying for. If you want more than ship in the base machine, they'll install another dozen pretty cheap. And the homebrew and design connections: They're sure not homebrew, and they're more than one designer can do. -- Mike Andrews Tired old sysadmin |
On Sat, 14 Aug 2004 18:24:14 +0100, John Woodgate wrote:
I read in sci.electronics.design that Keith wrote (in ) about 'Error in textbook?', on Sat, 14 Aug 2004: Unfortunately, boiling the CFC also distilled it, leaving any contamination on the chips. Sulfur hexafluoride might have been better, but it's probably more costly than CFCs were. Cost? Dunno. I do know that we were paying $50/qt (IIRC) for the stuff in '75. I wouldn't think a sulfur/fluoride brew could be made any "cleaner" than CFCs. THe problem was the contaminants. -- Keith |
On Sat, 14 Aug 2004 20:53:24 +0000, Mike Andrews wrote:
In (rec.radio.amateur.homebrew), Keith wrote: Unfortunately, boiling the CFC also distilled it, leaving any contamination on the chips. The result came to be known as the "black plague". Because of the "black plague" the "LEM" (Liquid Encapsulated Module) was replaced by a similar looking (though shorter) "TCM" (Thermal Conduction Module) which used pistons on the backside of the chips (increased to 121 chips) to transfer heat (10W per chip, 1200W total) to the cold-plate and filled with helium. The TCMs were used throught the '80s and early '90s for the high-end ECL systems. Yep. I've got a TCM somewhere at home; I need to take a pic of it for my web page. IIRC, it has 1024 pins, and the largest ZIF socket I've ever seen. I think you'll count a lot more than 1024 pins. The ones I worked on int the '70s had 1800. There were 1280 signal pins (I rember that name because of the logic tester - the LT1280). The cold plate on the TCM is about 4.5" square, very smooth, and designed to go on a larger water-cooled manifold with some dozens more TCMs, all getting water from a chiller. Twelve TCMs for each processor, and nine for each channel (for the 3080s). A system could have upwards of a hundred of these beasts in it. Later sytems had fewer since the logic density increased. ...which is what ultmately killed them. The infrastructure was simply too expensive for the quantity needed. They're called "wet-frame" machines by a lot of us who dealt with them, and especially by those of us who had a leak develop somewhere in the cooling system. ****ers, eh? I was once tasked to design a "leak detector" for exactly thi sproblem. I brought in the guts out of a toilet (complete with copper float) and told them to put these under the floor with a switch. Come on! Detect a leak in a pipe a few hundred feet long passing many gallons per minute? Nowadays one TCM's circuitry fits on a single chip, at a meager fraction of the TCM's dissipation, and is enormously faster, so that (for 9672 hardware, anyway) Note that the first CMOS machines were slower than those they replaced (in direct violation of IBM's "prime Directive"). THough they were significantly cheaper and with more processors (loophole alert). IBM ships the machine with a bunch of CPUs and licenses you the code to turn on as many as you're paying for. If you want more than ship in the base machine, they'll install another dozen pretty cheap. "Install"? ;-) They'll enable as many as you want, for as long as you are paying. We called this "Rent-A-MIP". THere is even a crypto unit in there if you want to use it. And the homebrew and design connections: They're sure not homebrew, and they're more than one designer can do. Yeah, there were a few designers doing this stuff. ;-) -- Keith |
Keith wrote:
On Sat, 14 Aug 2004 18:24:14 +0100, John Woodgate wrote: I read in sci.electronics.design that Keith wrote (in ) about 'Error in textbook?', on Sat, 14 Aug 2004: Unfortunately, boiling the CFC also distilled it, leaving any contamination on the chips. Sulfur hexafluoride might have been better, but it's probably more costly than CFCs were. Cost? Dunno. I do know that we were paying $50/qt (IIRC) for the stuff in '75. I wouldn't think a sulfur/fluoride brew could be made any "cleaner" than CFCs. THe problem was the contaminants. Yeah, and whether you're working with a liquid or gas, it's the contaminants that make it dirty. I'd think a gas could be cleaner already just by not dissolving a bunch of solids, although the solids in suspension can be even smaller than in a liquid. But those aren't going to condense out. They might collect as dust, but if that's your problem, then you have a lot worse problem than contaminated fluid! I guess my point is, it wasn't the CFC's fault that it was contaminated. And, FYI, AIUI, SF6 is really quite inert. You make it sound like fire and brimstone, for heaven's sakes! ;-) But it has raised a good question - which makes a better heat transfer agent? Helium or SF6? (gases only, of course ;-) ) Cheers! Rich |
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