Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.
--

"What is now proved was once only imagin'd." - William Blake, 1793.

On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge
wrote:

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John

On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge
wrote:

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.


Oh, the skin depth equation on p 10 is apparently wrong, too.

John

On Wed, 11 Aug 2004 13:01:51 -0700, John Larkin
wrote:


Oh, the skin depth equation on p 10 is apparently wrong, too.

Excellent, John. Many thanks. It's reassuring you've seen the actual
book for yourself, but it would have been better if you'd have hung
fire until Active8 or someone else impulsive jumped in and accused me
of getting it all wrong. There are quite a few stoopid errors in this
otherwise excellent book. This one was just a bit more obvious than
the others. :-)
Thanks again for the prompt response.

--

"What is now proved was once only imagin'd." - William Blake, 1793.

Hi Paul,

Seems like it was meant for a MOSFET or someone typeset a wrong resistor
value and then all this got lost in the review process. Probably best to
let the author know so he can correct in the next ed.

What is now proved was once only imagin'd." - William Blake, 1793.

I like this one! It reminds me of a mechanical engineering book I got from my late father in law, a book he received from someone even more senior. Under radio frequency waves it states that this is a wonderous and strange phenomenon that is yet to be explaineth. And here I am an RF guy...

Regards, Joerg

http://www.analogconsultants.com

"Paul Burridge" wrote in message
...
Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

Have a look on the inside flap to see if he's a reader in engineering at
some University. If so, then they probably are errors.



p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.
--

"What is now proved was once only imagin'd." - William Blake, 1793.

John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

On Thu, 12 Aug 2004 02:58:57 GMT, Fred Bloggs
wrote:



John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....


Good point. Bowick seems to be applying the jfet gate-voltage equation
backwards to enhance it! The other example on page 120 is even
sillier.

Just shows you that an RF expert can't always handle DC.

John

On Wed, 11 Aug 2004 21:19:04 +0100, Paul Burridge wrote:

On Wed, 11 Aug 2004 13:01:51 -0700, John Larkin
wrote:

Oh, the skin depth equation on p 10 is apparently wrong, too.

Excellent, John. Many thanks. It's reassuring you've seen the actual
book for yourself, but it would have been better if you'd have hung
fire until Active8 or someone else impulsive jumped in and accused me
of getting it all wrong. There are quite a few stoopid errors in this
otherwise excellent book. This one was just a bit more obvious than
the others. :-)
Thanks again for the prompt response.

Hey POS troll. How would you see it if I'm kill filed?
--
No Regards,
Mike

On 12 Aug 2004 17:41:08 GMT, (John Crabtree) wrote:

Do you have the original edition ca. 1983, or what amazon.com descibes as the
Newnes Reprint edition of 1997 ?

I too have seen mistakes in the 1983 edition. It would be a pity if these were
not corrected in the reprint. Does any body have good information on this ?

My copy's the later one (but it's already looking very much older):-)
--

"What is now proved was once only imagin'd." - William Blake, 1793.