Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.
--

"What is now proved was once only imagin'd." - William Blake, 1793.

On Wed, 11 Aug 2004 20:46:24 +0100, Paul Burridge
wrote:

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John

John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

On Thu, 12 Aug 2004 02:58:57 GMT, Fred Bloggs
wrote:



John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....


Good point. Bowick seems to be applying the jfet gate-voltage equation
backwards to enhance it! The other example on page 120 is even
sillier.

Just shows you that an RF expert can't always handle DC.

John

On Thu, 12 Aug 2004 08:28:41 -0700, John Larkin wrote:

On Thu, 12 Aug 2004 02:58:57 GMT, Fred Bloggs
wrote:



John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

LOL. That was an astute observation, not that I'm surprised. Either
I didn't read that part of the book ( I have a NOV '82 Siliconix
data book that sufficed) or I blew it off.

Good point. Bowick seems to be applying the jfet gate-voltage equation
backwards to enhance it! The other example on page 120 is even
sillier.

I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small
values of 2.48, yup. I better compare all his refs to my own
collection of app notes in der future and check the math.

Just shows you that an RF expert can't always handle DC.


It's his math, actually. See my other post and while you're at it,
reply to my reply to the idiot so he can see it. A blank post will
suffice -)

--
Best Regards,
Mike

On Thu, 12 Aug 2004 18:57:34 -0400, Active8
wrote:


I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small
values of 2.48, yup.

Now *that's* funny!

Too bad Paul won't see it!

John

In article ,
Fred Bloggs wrote:


John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.


--
--
forging knowledge

On Fri, 13 Aug 2004 03:49:15 +0000 (UTC),
(Ken Smith) wrote:

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.

How many mS did the Fet last? I suppose you could always stand there
with a can of arctic spray directed on it, but I doubt the customer
would be impressed. ;-)
--

"What is now proved was once only imagin'd." - William Blake, 1793.

Paul Burridge wrote:
On Fri, 13 Aug 2004 03:49:15 +0000 (UTC),
(Ken Smith) wrote:


Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.


How many mS did the Fet last? I suppose you could always stand there
with a can of arctic spray directed on it, but I doubt the customer
would be impressed. ;-)

Actually there have been systems produced that did run quite hot and
were arranged with a liquid nitrogen drip onto the electronics to keep
things cool.

On Fri, 13 Aug 2004 03:49:15 +0000 (UTC),
(Ken Smith) wrote:

In article ,
Fred Bloggs wrote:


John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.



Jfets make pretty good pA-leakage diodes, although the series
resistance tends to be higher than for a "real" diode. Never tried one
as a power rectifier.

Jfets don't enhance much, but gaasfets - especially phemts - enhance a
lot, typically 1.6 * Idss just before the gate begins conducting in
earnest. That can be useful.

John