Hi.

Thanks for your suggestions....

Yes, I'm trying to do some digital control to the frequency of LO using
the LTC part. I will think in another way to do that...

I'm looking for an oscillator of about 33MHz to replace the LTC part...
any ideas ?

About the AD607 comment, I have a voltage divider to couple the
previous LO output to the level of LO input of AD607... is it what you
mean ?

Thanks

Hern=E1n S=E1nchez

Hi again.

One last question (for this thread) about jitter... how low it needs to
be ? The LTC6903 datasheet says it's 1% (max value).

Thanks

Hern=E1n S=E1nchez

nanchez wrote:
Hi again.

One last question (for this thread) about jitter... how low it needs to
be ? The LTC6903 datasheet says it's 1% (max value).

Thanks

Hern=E1n S=E1nchez

Because I work with high-speed ADCs, I'm most familiar with articles
about jitter in sampled systems. A sampler and a mixer are pretty
similar, and you should be able to learn a lot from things like Analog
Devices ap notes AN-501 and AN-756, and even the data sheets for
converters like the AD6644 and AD6645. For example, the SNR for an
AD6644 sampling a 30MHz sinewave at 65Msamples/sec is degraded
perceptably by clock jitter of 0.15psec, which is about 0.001% jitter,
expressed as a percentage of the clock period.

I'd post links to the pdf files for those ap notes, but the form I have
them in, they are too long to reliably include in a posting. Just go
to http://www.analog.com/en/index.html and enter AN-501 or AN-756 into
the search box. Also, if you enter "jitter phase noise" (without the
quotes) into a Google search, you'll get LOTS of references.

http://www.maxim-ic.com/appnotes.cfm...te_number/3359 is an ap note
on conversion between clock jitter and phase noise.

Disclaimer: I have not reviewed any of these apnotes critically for
accuracy.

Cheers,
Tom

Yes, a voltage divider should do fine. It may be convenient to have
the voltage divider output look approximately like a 50-ohm source, but
from what I can see in the AD607 data sheet, there is no requirement
that the LO come from a 50 ohm source. You just want to deliver a
voltage to the LO input pin which is equivalent to -16dBm across a 50
ohm resistor: in other words, about 35mV RMS or 0.1V peak-to-peak. I
expect that if your level is anywhere between 0.1Vp-p and 0.2Vp-p, or
even more, or perhaps even a bit less than 0.1, it should work fine. I
didn't notice anything very explicit in the data sheet. about it.

Two choices for digitally-controlled LO are DDS (direct digital
synthesis) and PLL (phase locked loop). Each has its strong points and
drawbacks. Do you want to keep the power very low? What sort of
frequency resolution do you want? How simple do you need to keep the
circuit? How critical is it that the LO not have any noticable
spurious outputs? -- I still suspect that the QRP community has already
done some nice work on LOs that might suit your need.

Cheers,
Tom