Yes, a voltage divider should do fine. It may be convenient to have
the voltage divider output look approximately like a 50-ohm source, but
from what I can see in the AD607 data sheet, there is no requirement
that the LO come from a 50 ohm source. You just want to deliver a
voltage to the LO input pin which is equivalent to -16dBm across a 50
ohm resistor: in other words, about 35mV RMS or 0.1V peak-to-peak. I
expect that if your level is anywhere between 0.1Vp-p and 0.2Vp-p, or
even more, or perhaps even a bit less than 0.1, it should work fine. I
didn't notice anything very explicit in the data sheet. about it.

Two choices for digitally-controlled LO are DDS (direct digital
synthesis) and PLL (phase locked loop). Each has its strong points and
drawbacks. Do you want to keep the power very low? What sort of
frequency resolution do you want? How simple do you need to keep the
circuit? How critical is it that the LO not have any noticable
spurious outputs? -- I still suspect that the QRP community has already
done some nice work on LOs that might suit your need.

Cheers,
Tom