Hi,

The databook shows that the input is capacitive below 180MHz and down to
130MHz (3.18-j4.3). Extending the line on the smith chart it appears that the
input gets more capacitive at 70MHz. My understanding was that a capacitive
input would be counter-acted using a series inductor, however the original
amplifier clearly had a capacitor from base to ground. In PW April 96 I
stumbled across a 50MHz linear amplifier based on a 2N6080 and 2N6082 combo
(TA6U2 from Spectrum Communications - which may still be available today). For
both stages there is 1nF of capacitance from base to ground. In a third design
for which I have the schematic a 2m amplifier using a 2N6080 as the first
stage also has capacitance from base to ground. I'm puzzled.

-So why in three seperate designs do I see large capacitance between the base
of the transistor and ground?

I don't think you have considered the low value of 'R' being
dealt with here. Translating 3.18-j4.3 @ 130MHz into a parallel
combo gives 8.99ohms||185pF (according to Agilent's AppCAD). Now
with pi-tank matching (possibly not the optimum method), you would
need a shunt capacitance of Xc = R/Q = 681pF using an arbitrary Q
of 5. So a capacitor of 497pF (half your 1nF) together with the
184pF of the device would do nicely.


Cheers - Joe