|
Biasing of Dual Gate Fets
Hi,
Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David |
Biasing of Dual Gate Fets
Hi David,
Some will ask what you are designing before they can give you an answer. FYI http://users.easystreet.com/w7zoi/lna50.htm Don David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. |
Biasing of Dual Gate Fets
David wrote:
Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr |
Biasing of Dual Gate Fets
Tim,
Thanks for the info. So, say I wanted to set the bias up at 10mA. I find the Vd/Id curve on the datasheet. If I have say a 8V power supply and decide to use a choke in the drain. This gives me Vd of around 8V. The curve indicates that VGs1 should be 0V and VGs2 = 4V. This means Rs would be 8/10mA = 800R. Where I am now confused is that VGS voltages are the Gate to source voltage. If the source voltage is 8V from the example above then to get VGS2 of 4V then the bias on VG2 would need to be 12V ? Also if VGs1 = 0V then the actual voltage on G1 should be 4V ? Is this correct or am I misinterpreting something here ? Thanks. Regards David tim gorman wrote: David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr |
Biasing of Dual Gate Fets
OK, I think I got it.
Let's say I want Vdd = 8V. Say I have an RF chock in the Drain then Vds is almost 8V. Say I want 5mA bias current. I look at the Vds vs Id and find that VG1-s = -0.2V for this condition. (So actual VDs is 7.8V) Next I use a source resistor of VG1-s/ Id = 40 Ohms As VG1 = VG1-s + VG1 - IDxRS the Gate voltage applied is 0V. The graph on the datasheet mentions that this is the output when VG2-s is 4V. So now I calculate VG2 = VG2-s + ID x RS = 4.2V I suppose that I can make Rs smaller to the point where VG1-s is 0V on the graph.(Occurs at 10mA for BF998). If I want higher Q point I then add positive bias to V1. I also understand I can get around 10dB attenuation by lowering VG2-s from 4.2V towards 0V but need to make it negative if I want to switch the signal off altogether (If I was to use the FET as say a ASK or OOK modulator). Thanks tim gorman wrote: David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr |
Biasing of Dual Gate Fets
David wrote:
Tim, Thanks for the info. So, say I wanted to set the bias up at 10mA. I find the Vd/Id curve on the datasheet. If I have say a 8V power supply and decide to use a choke in the drain. This gives me Vd of around 8V. The curve indicates that VGs1 should be 0V and VGs2 = 4V. This means Rs would be 8/10mA = 800R. Where I am now confused is that VGS voltages are the Gate to source voltage. If the source voltage is 8V from the example above then to get VGS2 of 4V then the bias on VG2 would need to be 12V ? Also if VGs1 = 0V then the actual voltage on G1 should be 4V ? Is this correct or am I misinterpreting something here ? Thanks. Regards David tim gorman wrote: David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr I'm sorry, I should have picked up on the fact that you are using a dual-gate mosfet. A dual-gate mosfet is a lot like 2 fet's in series. Gate2 is usually used with an external bias to set the dynamic range of the device. The signal is usually associated with Gate1. You can apply a fixed bias to Gate2 or tie in something like an AGC signal to vary the device amplification. For this type of device you probably would be better off looking at the graph of the Transfer Characteristics. The graph will show the change in Id for changes in Vgs1 with Vgs2 at a fixed value. For your device I would probably run Vgs2 at 3v to 4v. Looking at the transfer graph, you would want Vgs2 to be around 0.1v to get in the middle of the linear curve. That would put your standing Id at about 9-11 mA. This would make your source resistor 0.1v/10mA = 10R. Remember that you'll want to breadboard the circuit and try this out before actually including it in a production unit. Use a fixed voltage divider to get the 4v for Vgs2 and a source resistor of 10R and see how the circuit works. You can always change the source resistor to get what you need. tim ab0wr |
Biasing of Dual Gate Fets
Tim,
Say we look at VG1s = 0.1V as per your example. The graph for BF998 shows that if VG2s = 4V and VDs = 8V then ID approx = 12.5mA This would mean that unless I applied a negative voltage on the source I would need to apply 0.1V forward bias to G1 and 4V to G2 ? As Rs is creating a negative self bias voltage ? If I set the bias point lower - say 5mA then VG1s is approx. -0.2V according to the graph. I can achieve this by using a resistor in the source of 0.2/5mA (40 Ohms) and then set VG1 = 0 (so that VG1s = -0.2V) and then 4.2V on G2 so that VG2s = 4V. Is this correct ? The transfer characteristic curve shows that for say 10mA. If VG2s = 4V then gm = around 24mS and if VG2s is reduced to 0V the gm reduces to about 7mS. Thanks regards David tim gorman wrote: David wrote: Tim, Thanks for the info. So, say I wanted to set the bias up at 10mA. I find the Vd/Id curve on the datasheet. If I have say a 8V power supply and decide to use a choke in the drain. This gives me Vd of around 8V. The curve indicates that VGs1 should be 0V and VGs2 = 4V. This means Rs would be 8/10mA = 800R. Where I am now confused is that VGS voltages are the Gate to source voltage. If the source voltage is 8V from the example above then to get VGS2 of 4V then the bias on VG2 would need to be 12V ? Also if VGs1 = 0V then the actual voltage on G1 should be 4V ? Is this correct or am I misinterpreting something here ? Thanks. Regards David tim gorman wrote: David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr I'm sorry, I should have picked up on the fact that you are using a dual-gate mosfet. A dual-gate mosfet is a lot like 2 fet's in series. Gate2 is usually used with an external bias to set the dynamic range of the device. The signal is usually associated with Gate1. You can apply a fixed bias to Gate2 or tie in something like an AGC signal to vary the device amplification. For this type of device you probably would be better off looking at the graph of the Transfer Characteristics. The graph will show the change in Id for changes in Vgs1 with Vgs2 at a fixed value. For your device I would probably run Vgs2 at 3v to 4v. Looking at the transfer graph, you would want Vgs2 to be around 0.1v to get in the middle of the linear curve. That would put your standing Id at about 9-11 mA. This would make your source resistor 0.1v/10mA = 10R. Remember that you'll want to breadboard the circuit and try this out before actually including it in a production unit. Use a fixed voltage divider to get the 4v for Vgs2 and a source resistor of 10R and see how the circuit works. You can always change the source resistor to get what you need. tim ab0wr |
Biasing of Dual Gate Fets
The problem with using FETs of all kinds is the wide part-to-part
variation. Look at the specs for the BF998 - many of the critical specs show only a maximum or minimum, but not both, or just a typical value. You can be way off if you simply use a "typical" set of curves. If you want to do an analytical design with a part with non-specifications like this is to use a curve tracer to generate curves for the individual part, then use those curves for your design. Pull another part of the same part number from your drawer, and you'll need a different design. This exercise is useful for educational purposes, but it isn't a technique you can use to design something that can be easily duplicated. That's probably why you don't see a lot of FETs being used in commercial products, except in applications where there's a lot of feedback to stabilize the operating point, such as source followers, or when simply nothing else will do. Even then, the manufacturer has probably paid the vendor to select parts with a much narrower, and well specified, range of characteristic values. That's been my experience in designing commercial electronic test equipment. Roy Lewallen, W7EL David wrote: Tim, Say we look at VG1s = 0.1V as per your example. The graph for BF998 shows that if VG2s = 4V and VDs = 8V then ID approx = 12.5mA This would mean that unless I applied a negative voltage on the source I would need to apply 0.1V forward bias to G1 and 4V to G2 ? As Rs is creating a negative self bias voltage ? If I set the bias point lower - say 5mA then VG1s is approx. -0.2V according to the graph. I can achieve this by using a resistor in the source of 0.2/5mA (40 Ohms) and then set VG1 = 0 (so that VG1s = -0.2V) and then 4.2V on G2 so that VG2s = 4V. Is this correct ? The transfer characteristic curve shows that for say 10mA. If VG2s = 4V then gm = around 24mS and if VG2s is reduced to 0V the gm reduces to about 7mS. Thanks regards David |
Biasing of Dual Gate Fets
What you say makes sense. Breadboard up a circuit and see what your idle
point winds up being. That's really the only way you will find out for sure. tim ab0wr David wrote: Tim, Say we look at VG1s = 0.1V as per your example. The graph for BF998 shows that if VG2s = 4V and VDs = 8V then ID approx = 12.5mA This would mean that unless I applied a negative voltage on the source I would need to apply 0.1V forward bias to G1 and 4V to G2 ? As Rs is creating a negative self bias voltage ? If I set the bias point lower - say 5mA then VG1s is approx. -0.2V according to the graph. I can achieve this by using a resistor in the source of 0.2/5mA (40 Ohms) and then set VG1 = 0 (so that VG1s = -0.2V) and then 4.2V on G2 so that VG2s = 4V. Is this correct ? The transfer characteristic curve shows that for say 10mA. If VG2s = 4V then gm = around 24mS and if VG2s is reduced to 0V the gm reduces to about 7mS. Thanks regards David tim gorman wrote: David wrote: Tim, Thanks for the info. So, say I wanted to set the bias up at 10mA. I find the Vd/Id curve on the datasheet. If I have say a 8V power supply and decide to use a choke in the drain. This gives me Vd of around 8V. The curve indicates that VGs1 should be 0V and VGs2 = 4V. This means Rs would be 8/10mA = 800R. Where I am now confused is that VGS voltages are the Gate to source voltage. If the source voltage is 8V from the example above then to get VGS2 of 4V then the bias on VG2 would need to be 12V ? Also if VGs1 = 0V then the actual voltage on G1 should be 4V ? Is this correct or am I misinterpreting something here ? Thanks. Regards David tim gorman wrote: David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr I'm sorry, I should have picked up on the fact that you are using a dual-gate mosfet. A dual-gate mosfet is a lot like 2 fet's in series. Gate2 is usually used with an external bias to set the dynamic range of the device. The signal is usually associated with Gate1. You can apply a fixed bias to Gate2 or tie in something like an AGC signal to vary the device amplification. For this type of device you probably would be better off looking at the graph of the Transfer Characteristics. The graph will show the change in Id for changes in Vgs1 with Vgs2 at a fixed value. For your device I would probably run Vgs2 at 3v to 4v. Looking at the transfer graph, you would want Vgs2 to be around 0.1v to get in the middle of the linear curve. That would put your standing Id at about 9-11 mA. This would make your source resistor 0.1v/10mA = 10R. Remember that you'll want to breadboard the circuit and try this out before actually including it in a production unit. Use a fixed voltage divider to get the 4v for Vgs2 and a source resistor of 10R and see how the circuit works. You can always change the source resistor to get what you need. tim ab0wr |
Biasing of Dual Gate Fets
Roy,
So if I had an adjustment on VG2 for each circuit and adjust for required Drain current on each product ? What's the consensus regarding Common Base BJT as LNA ? Thanks Regards David Roy Lewallen wrote: The problem with using FETs of all kinds is the wide part-to-part variation. Look at the specs for the BF998 - many of the critical specs show only a maximum or minimum, but not both, or just a typical value. You can be way off if you simply use a "typical" set of curves. If you want to do an analytical design with a part with non-specifications like this is to use a curve tracer to generate curves for the individual part, then use those curves for your design. Pull another part of the same part number from your drawer, and you'll need a different design. This exercise is useful for educational purposes, but it isn't a technique you can use to design something that can be easily duplicated. That's probably why you don't see a lot of FETs being used in commercial products, except in applications where there's a lot of feedback to stabilize the operating point, such as source followers, or when simply nothing else will do. Even then, the manufacturer has probably paid the vendor to select parts with a much narrower, and well specified, range of characteristic values. That's been my experience in designing commercial electronic test equipment. Roy Lewallen, W7EL David wrote: Tim, Say we look at VG1s = 0.1V as per your example. The graph for BF998 shows that if VG2s = 4V and VDs = 8V then ID approx = 12.5mA This would mean that unless I applied a negative voltage on the source I would need to apply 0.1V forward bias to G1 and 4V to G2 ? As Rs is creating a negative self bias voltage ? If I set the bias point lower - say 5mA then VG1s is approx. -0.2V according to the graph. I can achieve this by using a resistor in the source of 0.2/5mA (40 Ohms) and then set VG1 = 0 (so that VG1s = -0.2V) and then 4.2V on G2 so that VG2s = 4V. Is this correct ? The transfer characteristic curve shows that for say 10mA. If VG2s = 4V then gm = around 24mS and if VG2s is reduced to 0V the gm reduces to about 7mS. Thanks regards David |
Biasing of Dual Gate Fets
On Fri, 28 Jul 2006 06:08:01 GMT, David
wrote: Roy, So if I had an adjustment on VG2 for each circuit and adjust for required Drain current on each product ? Or pick a set of bogy values and accept there will be a range of operating current. I've found DGmosFET perfomance is not greatly impacted by variations in Idss and Gm for practical circuits. What's the consensus regarding Common Base BJT as LNA ? Hard matching the input at any decent current, at 4-5ma the input R is around 5 ohms. Easily overloaded as a result of usually being used at low current to make the match easier. It's feature is fair stability and the device is working at at it's alpha cutoff frequency. The latter was more important 30 years ago when UHF transistors were harder to get. Noise performance was dependent on device but even in 1972 I could get TIMX10s down to around 1.5DB at 450mhz. Allison Thanks Regards David Roy Lewallen wrote: The problem with using FETs of all kinds is the wide part-to-part variation. Look at the specs for the BF998 - many of the critical specs show only a maximum or minimum, but not both, or just a typical value. You can be way off if you simply use a "typical" set of curves. If you want to do an analytical design with a part with non-specifications like this is to use a curve tracer to generate curves for the individual part, then use those curves for your design. Pull another part of the same part number from your drawer, and you'll need a different design. This exercise is useful for educational purposes, but it isn't a technique you can use to design something that can be easily duplicated. That's probably why you don't see a lot of FETs being used in commercial products, except in applications where there's a lot of feedback to stabilize the operating point, such as source followers, or when simply nothing else will do. Even then, the manufacturer has probably paid the vendor to select parts with a much narrower, and well specified, range of characteristic values. That's been my experience in designing commercial electronic test equipment. Roy Lewallen, W7EL David wrote: Tim, Say we look at VG1s = 0.1V as per your example. The graph for BF998 shows that if VG2s = 4V and VDs = 8V then ID approx = 12.5mA This would mean that unless I applied a negative voltage on the source I would need to apply 0.1V forward bias to G1 and 4V to G2 ? As Rs is creating a negative self bias voltage ? If I set the bias point lower - say 5mA then VG1s is approx. -0.2V according to the graph. I can achieve this by using a resistor in the source of 0.2/5mA (40 Ohms) and then set VG1 = 0 (so that VG1s = -0.2V) and then 4.2V on G2 so that VG2s = 4V. Is this correct ? The transfer characteristic curve shows that for say 10mA. If VG2s = 4V then gm = around 24mS and if VG2s is reduced to 0V the gm reduces to about 7mS. Thanks regards David |
Biasing of Dual Gate Fets
Sorry, I have almost no experience in using dual-gate MOSFETS, for the
reasons I mentioned. Beginning somewhere around the mid-80s, when manufacturing became highly automated, my employers strongly discouraged designs which included any adjustments. Besides the labor required to make the adjustment, the variable component lowered the product's reliability, so we'd often design in a lot of parts to get around having any tweaks. But individual adjustment is still a viable option for some products. What I don't know is whether you'd get satisfactory performance with widely differing devices all running at the same drain current. That would depend on your design and application. If you're considering making a product, I'd certainly do some modeling with extreme component parameters to see what happens. And you might consider some sort of device selection and/or incoming inspection or sorting to make sure you don't get any truly extreme parts. One thing to be careful about is that when a part is so poorly specified, other companies might be buying large numbers of selected parts. That leaves you with the leftovers. I've seen some really strange distributions resulting from this -- parts with extreme characteristics on both ends, but nothing anywhere near the "typical" values. It used to be common with zeners, until they got better at making -- 10% tolerance zeners would all be between 5 and 10% from nominal, in both directions, with none closer than 5%. Those had been selected out and sold as 5% tolerance parts. Just a few of the things I've picked up in 30 or so years as a design engineer. Roy Lewallen, W7EL David wrote: Roy, So if I had an adjustment on VG2 for each circuit and adjust for required Drain current on each product ? What's the consensus regarding Common Base BJT as LNA ? Thanks Regards David |
Biasing of Dual Gate Fets
Ah, but that's a model for just one BF998. The one you pull out of the
drawer might bear very little resemblance to it. Roy Lewallen, W7EL jack wrote: FWIW, I found the following SPICE model for the BF998 on the web -- note that the two MOSFETs VMAX are dissimilar, a lot of the entries are for parasitic elements: . . . |
Biasing of Dual Gate Fets
FWIW, I found the following SPICE model for the BF998 on the web -- note
that the two MOSFETs VMAX are dissimilar, a lot of the entries are for parasitic elements: * BF998 SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS * ENVELOPE SOT143 * 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1; ..SUBCKT BF998 1 2 3 4 L10 1 10 0.12N L20 2 20 0.12N L30 3 30 0.12N L40 4 40 0.12N L11 10 11 1.20N L21 20 21 1.20N L31 30 31 1.20N L41 40 41 1.20N C13 10 30 0.085P C14 10 40 0.085P C21 10 20 0.017P C23 20 30 0.085P C24 20 40 0.005P D11 42 11 ZENER D12 42 41 ZENER D21 32 11 ZENER D22 32 31 ZENER RS 10 12 100 MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6 MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6 ..MODEL ZENER D BV=10 CJO=1.2E-12 RS=10 ..MODEL GATE1 + NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9 + NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11 + ETA=0.06 KAPPA=2 LD=0.1E-6 + CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12 ..MODEL GATE2 + NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9 + NSUB=3E15 VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11 + ETA=0.06 KAPPA=2 LD=0.1E-6 + CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12 ..ENDS BF998 |
Biasing of Dual Gate Fets
In ancient times I set up a VHF amplifier test circuit with a dual-gate
3NXXX and measured gain and IM distortion vs bias parameters, DC feedback and negative RF feedback. I was able to compare many samples and found that I could get adequate (for my purposes) uniformity for a dozen samples in a particular application. The tradeoff is reduced gain to get "improved" uniformity. Trying to get max results from a single stage is not as good as two or three cascaded more modest stages. The cost of this approach is of course not minimal. The first stage dominates total noise figure. Bill W0IYH "David" wrote in message ... OK, I think I got it. Let's say I want Vdd = 8V. Say I have an RF chock in the Drain then Vds is almost 8V. Say I want 5mA bias current. I look at the Vds vs Id and find that VG1-s = -0.2V for this condition. (So actual VDs is 7.8V) Next I use a source resistor of VG1-s/ Id = 40 Ohms As VG1 = VG1-s + VG1 - IDxRS the Gate voltage applied is 0V. The graph on the datasheet mentions that this is the output when VG2-s is 4V. So now I calculate VG2 = VG2-s + ID x RS = 4.2V I suppose that I can make Rs smaller to the point where VG1-s is 0V on the graph.(Occurs at 10mA for BF998). If I want higher Q point I then add positive bias to V1. I also understand I can get around 10dB attenuation by lowering VG2-s from 4.2V towards 0V but need to make it negative if I want to switch the signal off altogether (If I was to use the FET as say a ASK or OOK modulator). Thanks tim gorman wrote: David wrote: Hi, Pretty fundamental I know but can someone please explain the steps for setting up bias for a Dual Gate MOSFET. I know I could place a pot on the gate and source for each circuit and play with values but I would like a method that enables me to calculate the values. The main issue is how to determine values for Rs and Gate 2 Voltage. I am using BF998 and want to have a "play" at 5V and 8V supply. The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2 But Idss is stated as 2-18mA Vp Gate 1 is given as a range from 1-2V Vp gate 2 is given as range from 0.5 to 1.5V If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at the source to determine Vgs ? Any help much appreciated. Regards David One way of doing this is to get the datasheet for the FET you are using. There should be a graph that shows the operating characteristic curves. The x-axis will be Vds and the Y-axis will be the drain current Id. The characteristic curves will be for various levels of Vgs. Pick an operating point based on the type of amplifier you want. Let's suppose it will be Class A. Assume the FET has a power supply voltage of 40v and an Idss of 10ma. Let's say that you pick a point in the middle of the operating curves that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing out of the amplifer. Looking at the characteristic curves shows that this will require a Vgs of about -1v. Now you have everything you need. If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor you see in FET amps is not really there for biasing but more to set the input impedance of the amplifier. As long as the leakage current from the gate to the source is small, Vgs is set by the bias resistor in the source lead. tim ab0wr |
Biasing of Dual Gate Fets
On Sat, 29 Jul 2006 00:00:12 -0700, Roy Lewallen
wrote: Sorry, I have almost no experience in using dual-gate MOSFETS, for the reasons I mentioned. Beginning somewhere around the mid-80s, when manufacturing became highly automated, my employers strongly discouraged designs which included any adjustments. Besides the labor required to make the adjustment, the variable component lowered the product's reliability, so we'd often design in a lot of parts to get around having any tweaks. But individual adjustment is still a viable option for some products. What I don't know is whether you'd get satisfactory performance with widely differing devices all running at the same drain current. That would depend on your design and application. If you're considering making a product, I'd certainly do some modeling with extreme component parameters to see what happens. And you might consider some sort of device selection and/or incoming inspection or sorting to make sure you don't get any truly extreme parts. One thing to be careful about is that when a part is so poorly specified, other companies might be buying large numbers of selected parts. That leaves you with the leftovers. I've seen some really strange distributions resulting from this -- parts with extreme characteristics on both ends, but nothing anywhere near the "typical" values. It used to be common with zeners, until they got better at making -- 10% tolerance zeners would all be between 5 and 10% from nominal, in both directions, with none closer than 5%. Those had been selected out and sold as 5% tolerance parts. Just a few of the things I've picked up in 30 or so years as a design engineer. Roy Lewallen, W7EL Roy, There are a large number of VHF and HF radios both past and present that use the DGmosfets in place like the RF amp sometimes a balanced mixer. A recent example is the TenTec 526 (6n2) 6 and 2 meter radio as the RF amp. Another current example is the TT 1208 transverter also as RF amp. If your not pushing the device for max gain or ultimate IP3 possible they perform well and offer low noise for their power needs. Neither require pots or other tweaking (other than tuneable circuits). Can other deivces be used to do better, yes. But, engineering is always about understanding and compromize. I'd never use DGfets for something like a scope amp or other instrumentation where DC operating point or balance is a requirement. I have use them as a high impedence (1mohm) AGC'd input for high input senstivity frequency counters. Another place where I've used them is IF amps, they are just far easier to AGC than CA3020 or MC1350 and quieter. My favorite line from years back. Good, Fast, Cheap, Pick any two. Allison |
Biasing of Dual Gate Fets
Doesn't say much about their quality control if the devices are that
dissimilar. FWIW, I have developed a semiconductor and tube curve tracer for use within Multisim -- create the component in Multisim, plug it into the curve tracer, run the test and compare with the manufacturer's charts. I have also built a tube curve tracer -- same will apply for semiconductors -- even published an article on it. With this i can compare the characteristics of the device vis a vis mfr data sheet AND the simulation in EWB. Jack "Roy Lewallen" wrote in message ... Ah, but that's a model for just one BF998. The one you pull out of the drawer might bear very little resemblance to it. Roy Lewallen, W7EL jack wrote: FWIW, I found the following SPICE model for the BF998 on the web -- note that the two MOSFETs VMAX are dissimilar, a lot of the entries are for parasitic elements: . . . |
Biasing of Dual Gate Fets
In article ,
wrote: I'd never use DGfets for something like a scope amp or other instrumentation where DC operating point or balance is a requirement. Interestingly enough, in Jim Williams's book "The Art and Science of Analog Circuit Design", there's a chapter by Steve Roach of Tektronix, which shows the use of a BF996 consumer-grade dual gate FET in a 1GHz oscilloscope preamp. http://books.google.com/books?vid=IS...VGMx8v3yDD4at4 |
| All times are GMT +1. The time now is 12:43 PM. |
Powered by vBulletin® Copyright ©2000 - 2025, Jelsoft Enterprises Ltd.
RadioBanter.com