I'm considering building a DDS to use as a VFO. I've heard of concerns
about the close in spurs which can be a problem. However, I think I can
address the close in spurs caused by phase quantization. I should be
able to get those to the -120 dB ballpark. The spurs caused by
amplitude quantization would limited by the DAC which will be a lot
worse for higher sample rates. But -96 dB ballpark is not inconceivable.

--

Rick

"rickman" wrote in message ...

I'm considering building a DDS to use as a VFO. I've heard of concerns
about the close in spurs which can be a problem. However, I think I can
address the close in spurs caused by phase quantization. I should be
able to get those to the -120 dB ballpark. The spurs caused by
amplitude quantization would limited by the DAC which will be a lot
worse for higher sample rates. But -96 dB ballpark is not inconceivable.

================================================== =====

Sometime ago I tried to use a "straight" DDS for a project and found the
spurs, or more correctly the phase jitter, made it unusable. The exact
amount of jitter depended upon the exact division ratio and got worse as the
output frequency increased.

I found that feeding the output of the DDS into a PLL improved things
considerably and made it very usable.

Hope this helps

John

On 2/26/2016 7:42 AM, John wrote:


"rickman" wrote in message ...

I'm considering building a DDS to use as a VFO. I've heard of concerns
about the close in spurs which can be a problem. However, I think I can
address the close in spurs caused by phase quantization. I should be
able to get those to the -120 dB ballpark. The spurs caused by
amplitude quantization would limited by the DAC which will be a lot
worse for higher sample rates. But -96 dB ballpark is not inconceivable.

================================================== =====

Sometime ago I tried to use a "straight" DDS for a project and found the
spurs, or more correctly the phase jitter, made it unusable. The exact
amount of jitter depended upon the exact division ratio and got worse as
the output frequency increased.

I found that feeding the output of the DDS into a PLL improved things
considerably and made it very usable.

When you say division ratio you mean the value of the step size used to
increment the phase register? The output frequency is clock speed * N/M
where N is the step size value and M is the modulus of the phase register.

--

Rick