I usually go for less than one tenth of a wavelength for maximum spacing
between vias. I never lay out the vias on a grid. This is one of the things
I learned at one of the EMI/EMC classes I took at when I was working at
Rockwell-Collins. I understand that different folks have different
approaches to board design, and these different approaches do work well, my
approach has been ok, with boards I have been designing well up to 5GHz. I
do need to state that I am not the foremost expert in this field; I am just
a simple soul that is scratching the surface of the RF realm!


This sounds to me like the problem resonance was just moved to a
different frequency by removing vias. The solution should have been to
add more ground vias.

We did redo the board layout without increasing the number of vias. We
merely replaced them in a pseudo-random fashion, and the board didn't show
any resonances until we got up to 13GHz, which was well above the 1.8GHz
image band.
Originally, the vias were dropped on a 50 mil grid; 1/20 of a wavelength in
the 1.8GHz image band is 328 mils, so the distance between vias was well
within the desired window.


I¹m assuming the situation you are painting is a continuous ground
plane on the bottom with circuit features on the top of the board with
additional ground plane ³flood² on the top in a bid to provide more
isolation between circuit paths or just improving ground on the board.

To get patches of ground plane on the top of the board to behave the
same electrically as ground plane on the bottom the impedance must
remain low relative to the frequency of operation. To accomplish this a
number of vias must connect the patches or areas of ground plane on top
to the continuous ground plane on the bottom. The rule of thumb I use
is a 1/4 wave of the highest frequency of operation. The reason for the
1/4 wave is this is the minimum feature size that is likely to resonate
inadvertently in the design so for 900 MHz that would be about ~ 278 ps
for a 1/4 wave and at ~ 145 ps an inch for a FR4 type dielectric that
would be ~ 1.9 inches to propagate on the board. You don¹t want any
ground plane features on the board top to be any longer than 1.9 inches
without a via to the ground plane below.

I agree..............to do any less than this will result in unassociated
ground flood, resulting in a sympathetic radiator.


For example lets say you pick a via spacing of 1 inch to be safe and
you have two circuit traces going two a mixer on the board. These two
traces start several inches apart on the board and gradually come to
about .5 inches of each other as they approach the mixer. If you put
ground plane between them it will look like a finger pointed at the
mixer and with 1-inch regular grid placement of the vias none might
have connected this finger to the ground plane below. This finger can
then behave as a 1/4-wave stub if it is 1.9 inches long. This can be
fixed by adding (at least) one via at the end of the finger to the
ground plane below lowering the impedance next to the mixer so it can¹t
move electrically.

At high frequencies, another good technique is to drop at least four vias on
the ground return leads of mixers, MMICs, etc
It looks like you have been in the industry for awhile!


A good way to check a PC board for undesired resonances is to take
the unpopulated board, and connect an SMA launch at each end of the
board (input and output). Connect a network analyzer, and you should
see a flat noise spectrum, if the board was properly designed.


I never thought of doing this. Thanks for the idea.

Anytime! This takes some of the guesswork out of the characterization. I
have even run into improperly designed boards, where the company was too
cheap to add another layer in the form of a power plane, and the power
distribution traces formed a resonant circuit. The designer thought that he
could drop some decoupling capacitors along the power traces, not realizing
that he was creating a transmission line filter up in the microwave region.


Another trick of the trade for checking VCOs is to connect a network
analyzer to the inpur of the VCO. Set up the analyzer for a Smith
Chart type of display. You will know if you have your feedback
capacitors optimized for the tuning range of interest, if you are
centered in the maximum magnitude region of negative resistance. This
was a pretty common technique at Rockwell. When I mentioned this to
the folks that I was working with in my department at Motorola, they
had never heard of this method.

I think I understand what you are describing here but I need more detail
to be sure.

What this consists of is removing the resonator from the oscillator circuit,
leaving only the feedback capacitors (collpits circuit)
intact. Next, you connect a network analyzer to this input poing of the
circuit, and set it up for a Smith Chart response, viewing the S11
parameters. The trace you are interested in is the Unity Gain Circle. In the
frequency region where the circuit will function as an oscillator, you will
see a bit of negative resistance. As you adjust the value of Cequiv of the
feedback capacitors, you will see this region mover around. In this way, you
can optimize the circuit, seeing the changes in the imaginary terms.
Another cool thing about this technique is that you predict whether or not
the circuit will have a monotonic response (VCOs)
This negative resistance should be very smooth; if there a small squiggly
loops in the response, the response will not be monotonic. In other words,
if you were working with a VCO, and you had a tuning voltage of 2 to 5V, as
you increse the voltage from 2 to 5V, the frequency of the VCO should
increase at a rate determined by its KV characteristic.
If this isn't the case, for example, suppose you start out with a tuning
voltage of 2V; you will be starting at frequency F. As you increase the tune
voltage, the frequency should now be (F+X), but what can happen at some
tuning voltages is that you actually see the frequency decrease slightly,
only to increase again as you continue to increase the tuning voltage. In
other words, you can have two different tuning voltages that can invoke the
same frequency from the VCO!
Can you imaging trying to design a predictable PLL when this happens?
Oh, one more thing........................about those board resonances that
we were talking about. There was one microwave synthesizer board that I was
characterizing for spurs several years back. All of the spurs were
below -70dBc, but as soon as the unit was installed into the enclosure, the
3rd harmonic rose to -30dBc. This board was mounted on bosses in about 15
different places. I discovered that when I loosened one of the mounting
screws in the middle of the PC board, and adjusted the tension on the screw,
I could use it like a trimmer to null the harmonic down to the original
level. I never did figure out what was going on, and we eventually decided
to place a piece of Kapton tape on the underside of the board, and use a
nylon screw in this location. I did try that RF absorbing foam, and even
that didn't work.
I do realize that this really wasn't a cure..............an old friend of
mine put it perfectly; a problem board is like a water ballon. If you push
into the balloon at one point, it bulges out in another direction. In like
manner, a simple change to change a resonance in one point of the board can
cause another resonance in another part of the board, if the board isn't
designed properly.
Unfortunately, sometimes these problems don't show up until it is too late.
Thanks for the input!

Pete

--
Telamon
Ventura, California