Hi Tim,
the serial data are clocked beginning with the LSB up to MSB and the
control word ends the sequence. It is legal to issue e.g. one or two
bytes followed by the FQ_UD pulse for fine tuning. Did you try it ?
I have had a similar experience with AD9851, which IMHO uses the same
protocol. The error was in the firmware routine sending serial data
and W_CLK to the port, not in the DDS chip.

BR from Ivan


"Tim" wrote in message ...
No, I'm tasting gun metal yet but if you are experienced with the AD9850 DDS
please read on.

I am clocking out 40 bits serially to the unit, data word + control, for
some reason the DDS only updates the output freq based on the results of the
first 16 bits. When powered up the unit is stable, not misbehaving and seems
to respond with the exception of the last 16 bit freq bits. If the last 16
bits are set to 0 the output results are the same as when they are vaild.
It jumps about 600 hz or so instead of 10 hz

What has be scratching my head is that it must be "seeing" the last 16 bits
and control word or it wouldn't come alive. Has anyone any input on what may
be missing, similar problems? I clock out 32 bit freq control, then 8 bit
control word then a 10us wide F_update pulse. Again, stable, working but
ignoring last 16 bits.