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#1
October 17th 03, 06:20 AM
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AD9850 DDS - Help prevent suicide
No, I'm tasting gun metal yet but if you are experienced with the AD9850 DDS
please read on. I am clocking out 40 bits serially to the unit, data word + control, for some reason the DDS only updates the output freq based on the results of the first 16 bits. When powered up the unit is stable, not misbehaving and seems to respond with the exception of the last 16 bit freq bits. If the last 16 bits are set to 0 the output results are the same as when they are vaild. It jumps about 600 hz or so instead of 10 hz What has be scratching my head is that it must be "seeing" the last 16 bits and control word or it wouldn't come alive. Has anyone any input on what may be missing, similar problems? I clock out 32 bit freq control, then 8 bit control word then a 10us wide F_update pulse. Again, stable, working but ignoring last 16 bits. Using a PIC 16F73 and simultaneously dumping the 4, 8 bit words out the serial port I get: Changing freq starting with 7.10000 by 10 hz freq 7.10001 %00101101%01110000%10101000%00001000 freq 7.10002 %00101101%01110000%10101100%00111010 freq 7.10003 %00101101%01110000%10110000%01101100 freq 7.10004 %00101101%01110000%10110100%10011101 freq 7.10005 %00101101%01110000%10111000%11001111 freq 7.10006 %00101101%01110000%10111101%00000001 freq 7.10007 %00101101%01110000%11000001%00110011 freq 7.10008 %00101101%01110000%11000101%01100100 freq 7.10009 %00101101%01110000%11001001%10010110 freq 7.10010 %00101101%01110000%11001101%11001000 freq 7.10011 %00101101%01110000%11010001%11111010 freq 7.10012 %00101101%01110000%11010110%00101011 freq 7.10013 %00101101%01110000%11011010%01011101 freq 7.10014 %00101101%01110000%11011110%10001111 freq 7.10015 %00101101%01110000%11100010%11000001 freq 7.10016 %00101101%01110000%11100110%11110010 freq 7.10017 %00101101%01110000%11101011%00100100 freq 7.10018 %00101101%01110000%11101111%01010110 freq 7.10019 %00101101%01110000%11110011%10001000 freq 7.10020 %00101101%01110000%11110111%10111001 freq 7.10021 %00101101%01110000%11111011%11101011 freq 7.10022 %00101101%01110001%00000000%00011101 - audible change heard here and again when bit 16 rollsover to 0 again freq 7.10023 %00101101%01110001%00000100%01001111 freq 7.10024 %00101101%01110001%00001000%10000000 freq 7.10025 %00101101%01110001%00001100%10110010 freq 7.10026 %00101101%01110001%00010000%11100100 freq 7.10027 %00101101%01110001%00010101%00010110 freq 7.10028 %00101101%01110001%00011001%01000111 freq 7.10029 %00101101%01110001%00011101%01111001 freq 7.10030 %00101101%01110001%00100001%10101011 freq 7.10031 %00101101%01110001%00100101%11011100 freq 7.10032 %00101101%01110001%00101010%00001110 freq 7.10033 %00101101%01110001%00101110%01000000 freq 7.10034 %00101101%01110001%00110010%01110010 freq 7.10035 %00101101%01110001%00110110%10100011 freq 7.10036 %00101101%01110001%00111010%11010101 freq 7.10037 %00101101%01110001%00111111%00000111 freq 7.10038 %00101101%01110001%01000011%00111001 freq 7.10039 %00101101%01110001%01000111%01101010 freq 7.10040 %00101101%01110001%01001011%10011100 freq 7.10041 %00101101%01110001%01001111%11001110 freq 7.10042 %00101101%01110001%01010100%00000000 freq 7.10043 %00101101%01110001%01011000%00110001 freq 7.10044 %00101101%01110001%01011100%01100011 freq 7.10045 %00101101%01110001%01100000%10010101 freq 7.10046 %00101101%01110001%01100100%11000111 freq 7.10047 %00101101%01110001%01101000%11111000 freq 7.10048 %00101101%01110001%01101101%00101010 freq 7.10049 %00101101%01110001%01110001%01011100 freq 7.10050 %00101101%01110001%01110101%10001110 freq 7.10051 %00101101%01110001%01111001%10111111 freq 7.10052 %00101101%01110001%01111101%11110001 freq 7.10053 %00101101%01110001%10000010%00100011 freq 7.10054 %00101101%01110001%10000110%01010101 freq 7.10055 %00101101%01110001%10001010%10000110 freq 7.10056 %00101101%01110001%10001110%10111000 freq 7.10057 %00101101%01110001%10010010%11101010 freq 7.10058 %00101101%01110001%10010111%00011100 freq 7.10059 %00101101%01110001%10011011%01001101 freq 7.10060 %00101101%01110001%10011111%01111111 freq 7.10061 %00101101%01110001%10100011%10110001 freq 7.10062 %00101101%01110001%10100111%11100010 freq 7.10063 %00101101%01110001%10101100%00010100 freq 7.10064 %00101101%01110001%10110000%01000110 freq 7.10065 %00101101%01110001%10110100%01111000 freq 7.10066 %00101101%01110001%10111000%10101001 freq 7.10067 %00101101%01110001%10111100%11011011 freq 7.10068 %00101101%01110001%11000001%00001101 freq 7.10069 %00101101%01110001%11000101%00111111 freq 7.10070 %00101101%01110001%11001001%01110000 freq 7.10071 %00101101%01110001%11001101%10100010 freq 7.10072 %00101101%01110001%11010001%11010100 freq 7.10073 %00101101%01110001%11010110%00000110 freq 7.10074 %00101101%01110001%11011010%00110111 freq 7.10075 %00101101%01110001%11011110%01101001 freq 7.10076 %00101101%01110001%11100010%10011011 freq 7.10077 %00101101%01110001%11100110%11001101 freq 7.10078 %00101101%01110001%11101010%11111110 freq 7.10079 %00101101%01110001%11101111%00110000 freq 7.10080 %00101101%01110001%11110011%01100010 freq 7.10081 %00101101%01110001%11110111%10010100 freq 7.10082 %00101101%01110001%11111011%11000101 freq 7.10083 %00101101%01110001%11111111%11110111 freq 7.10084 %00101101%01110010%00000100%00101001 - again audible change in rx freq 7.10085 %00101101%01110010%00001000%01011011 freq 7.10086 %00101101%01110010%00001100%10001100 freq 7.10087 %00101101%01110010%00010000%10111110 freq 7.10088 %00101101%01110010%00010100%11110000 |
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#2
October 17th 03, 08:46 AM
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"Tim" wrote in message ... What has be scratching my head is that it must be "seeing" the last 16 bits and control word or it wouldn't come alive. Has anyone any input on what may be missing, similar problems? I clock out 32 bit freq control, then 8 bit control word then a 10us wide F_update pulse. Again, stable, working but ignoring last 16 bits. Sorry to bother the group, a typo in the source code was the problem. The DDS VFO is now smooth as silk... See you on 40m CW Tim |
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#3
October 23rd 03, 03:31 AM
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"Tim" writes:
Sorry to bother the group, a typo in the source code was the problem. The DDS VFO is now smooth as silk... See you on 40m CW Tim I have used most of AD's DDS chips. While their data sheets might be overwhelming, they are always correct-- so far. If you are having a problem it is generally because of a missed detail. Glad you found the problem. Steve -- Steven D. Swift, , http://www.novatech-instr.com NOVATECH INSTRUMENTS, INC. P.O. Box 55997 206.301.8986, fax 206.363.4367 Seattle, Washington 98155 USA |
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#4
October 23rd 03, 03:31 AM
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"Tim" writes:
Sorry to bother the group, a typo in the source code was the problem. The DDS VFO is now smooth as silk... See you on 40m CW Tim I have used most of AD's DDS chips. While their data sheets might be overwhelming, they are always correct-- so far. If you are having a problem it is generally because of a missed detail. Glad you found the problem. Steve -- Steven D. Swift, , http://www.novatech-instr.com NOVATECH INSTRUMENTS, INC. P.O. Box 55997 206.301.8986, fax 206.363.4367 Seattle, Washington 98155 USA |
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#5
October 17th 03, 08:39 AM
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Hi Tim,
the serial data are clocked beginning with the LSB up to MSB and the control word ends the sequence. It is legal to issue e.g. one or two bytes followed by the FQ_UD pulse for fine tuning. Did you try it ? I have had a similar experience with AD9851, which IMHO uses the same protocol. The error was in the firmware routine sending serial data and W_CLK to the port, not in the DDS chip. BR from Ivan "Tim" wrote in message ... No, I'm tasting gun metal yet but if you are experienced with the AD9850 DDS please read on. I am clocking out 40 bits serially to the unit, data word + control, for some reason the DDS only updates the output freq based on the results of the first 16 bits. When powered up the unit is stable, not misbehaving and seems to respond with the exception of the last 16 bit freq bits. If the last 16 bits are set to 0 the output results are the same as when they are vaild. It jumps about 600 hz or so instead of 10 hz What has be scratching my head is that it must be "seeing" the last 16 bits and control word or it wouldn't come alive. Has anyone any input on what may be missing, similar problems? I clock out 32 bit freq control, then 8 bit control word then a 10us wide F_update pulse. Again, stable, working but ignoring last 16 bits. |
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#6
October 17th 03, 08:46 AM
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"Tim" wrote in message ... What has be scratching my head is that it must be "seeing" the last 16 bits and control word or it wouldn't come alive. Has anyone any input on what may be missing, similar problems? I clock out 32 bit freq control, then 8 bit control word then a 10us wide F_update pulse. Again, stable, working but ignoring last 16 bits. Sorry to bother the group, a typo in the source code was the problem. The DDS VFO is now smooth as silk... See you on 40m CW Tim |
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#7
October 17th 03, 08:39 AM
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Hi Tim,
the serial data are clocked beginning with the LSB up to MSB and the control word ends the sequence. It is legal to issue e.g. one or two bytes followed by the FQ_UD pulse for fine tuning. Did you try it ? I have had a similar experience with AD9851, which IMHO uses the same protocol. The error was in the firmware routine sending serial data and W_CLK to the port, not in the DDS chip. BR from Ivan "Tim" wrote in message ... No, I'm tasting gun metal yet but if you are experienced with the AD9850 DDS please read on. I am clocking out 40 bits serially to the unit, data word + control, for some reason the DDS only updates the output freq based on the results of the first 16 bits. When powered up the unit is stable, not misbehaving and seems to respond with the exception of the last 16 bit freq bits. If the last 16 bits are set to 0 the output results are the same as when they are vaild. It jumps about 600 hz or so instead of 10 hz What has be scratching my head is that it must be "seeing" the last 16 bits and control word or it wouldn't come alive. Has anyone any input on what may be missing, similar problems? I clock out 32 bit freq control, then 8 bit control word then a 10us wide F_update pulse. Again, stable, working but ignoring last 16 bits. |
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