If anyone else has got the answer, come on, post !

Yes, that also sounds for me the best thing to do (improving buffer
between VCO and PLL). Well, I'm not experienced with such circuits, so
could you just explain how to bias the FET.


VCO o-||-- S-D --||--o OUT TO PLL
^ FET=MPF102 or stg like that
G
|
o----------------o GND


And one last thing, could you re-explain how you advise to shield the
FET ? I don't see what you mean :-(

Thanks for your answer ;-)