I've been struggling to really understand how FET buffers and simple FET
amplifiers work, since implementing a VCO buffer which didn't work.

I've recently read the Jan 2005 issue of Practical Wireless in which there is
an article regarding FET amplifiers.

Tonight I selected a 2N3819 FET and made various Vgs vs Id measurements and
plotted them in a table and a graph. I got the expected curve. Vpgs was around
-4V and Idss was 13mA.

I chose an operating point from the table of Id=4.1mA and Vgs=-2V and from
this calculated Rs and chose the nearest standard value of 470ohm.

I then breadboarded (in a 0.1" plug in board) a simple FET amplifier circuit
starting with Rg, Rs, the FET and an input decoupling capacitor of 1nF only. I
used a meter to measure Id. It was 4.3mA - near enough to the expected value
given the choice of the resistor. The source voltage was 2.0V. All as expected.

I then added Rd. Since Vdd was 10V (from a PSU and decoupled on the breadboard
with 220uF and 0.1uF) I selected 10-((10-2)/2) = 6V for the drain voltage to
allow a symmetrical output voltage swing. Rd was calculated and a value of 1k
was chosen.

Adding this component slightly changed the bias values. I assume that this is
because the Vgs vs Id function changes with Vdd which has now lowered from the
10V used when the plot was made to the current value of around 5.7V.

I then connected up a signal generator and set the frequency to 9MHz. For an
input swing of 2V pk-to-pk the output voltage was virtually the same. This is
where I have problems understanding exactly what is happening. I know that
since Rs is not decoupled there is negative feedback and Vgs will vary
slightly from the quiescent value. In doing so Id will change which should be
the same as Is which should modulate the output voltage. I have been trying to
visualise how the operating point is moving on the Vgs vs iD graph, but I am
not getting it.

When I add a decoupling capacitor of 1nF across Rs, I think that I understand
things better. Since the source voltage is now fixed for RF as the input
voltage changes Vgs is directly modulated and modulates Id. The PW article
explains that the gain should be gm * Rd. Using the table gm should be around
3.2mA/V for the bias values. Calculations say that the gain should be 0.0032 *
1000 = 3.2, but using a scope I see a gain of slightly over 2. Even for an
input of 2V pk-to-pk the output waveform is pretty good.

I'm puzzled with the discrepancy between measured values and calculated
values. Could the difference in the drain voltage between making the
measurements for the plot and the value used in the circuit be the reason? I
haven't gone back to re-plot the graph.

The circuit gain was consistent from a few MHz upto around 15MHz when it
dropped of considerably. Not bad for a breadboarded design connected with
wires of a few inches long. I don't know upto what frequency a properly built
circuit should operate upto.

I'm also thinking that I am at the limit of the input level that the circuit
can take (although I can't increase the value as it is already the maximum
from the sig gen). Since Vgs quiescent is -2V and Vpgs is -4V I suspect that
Vgs is swinging from -4V to 0V.

My interest in the input range is more relevant for the FET source follower
configuration. This was the one which originally failed due to trying to
buffer to large a voltage swing taken directly from the oscillator tuned
circuit. Again I was having difficulty figuring out just how large a voltage
swing this circuit could buffer.

Any pearls of wisdom would be much appreciated.

I've read all the usual texts but it obviously hasn't quite sunk in!
I've also Googled for relevant information, but I've yet to find a clearly
written explanation that I can understand 100%. Some texts make assumptions or
omit key details.

regards...

--Gary