I've been struggling to really understand how FET buffers and simple FET
amplifiers work, since implementing a VCO buffer which didn't work.

I've recently read the Jan 2005 issue of Practical Wireless in which there is
an article regarding FET amplifiers.

Tonight I selected a 2N3819 FET and made various Vgs vs Id measurements and
plotted them in a table and a graph. I got the expected curve. Vpgs was around
-4V and Idss was 13mA.

I chose an operating point from the table of Id=4.1mA and Vgs=-2V and from
this calculated Rs and chose the nearest standard value of 470ohm.

I then breadboarded (in a 0.1" plug in board) a simple FET amplifier circuit
starting with Rg, Rs, the FET and an input decoupling capacitor of 1nF only. I
used a meter to measure Id. It was 4.3mA - near enough to the expected value
given the choice of the resistor. The source voltage was 2.0V. All as expected.

I then added Rd. Since Vdd was 10V (from a PSU and decoupled on the breadboard
with 220uF and 0.1uF) I selected 10-((10-2)/2) = 6V for the drain voltage to
allow a symmetrical output voltage swing. Rd was calculated and a value of 1k
was chosen.

Adding this component slightly changed the bias values. I assume that this is
because the Vgs vs Id function changes with Vdd which has now lowered from the
10V used when the plot was made to the current value of around 5.7V.

I then connected up a signal generator and set the frequency to 9MHz. For an
input swing of 2V pk-to-pk the output voltage was virtually the same. This is
where I have problems understanding exactly what is happening. I know that
since Rs is not decoupled there is negative feedback and Vgs will vary
slightly from the quiescent value. In doing so Id will change which should be
the same as Is which should modulate the output voltage. I have been trying to
visualise how the operating point is moving on the Vgs vs iD graph, but I am
not getting it.

When I add a decoupling capacitor of 1nF across Rs, I think that I understand
things better. Since the source voltage is now fixed for RF as the input
voltage changes Vgs is directly modulated and modulates Id. The PW article
explains that the gain should be gm * Rd. Using the table gm should be around
3.2mA/V for the bias values. Calculations say that the gain should be 0.0032 *
1000 = 3.2, but using a scope I see a gain of slightly over 2. Even for an
input of 2V pk-to-pk the output waveform is pretty good.

I'm puzzled with the discrepancy between measured values and calculated
values. Could the difference in the drain voltage between making the
measurements for the plot and the value used in the circuit be the reason? I
haven't gone back to re-plot the graph.

The circuit gain was consistent from a few MHz upto around 15MHz when it
dropped of considerably. Not bad for a breadboarded design connected with
wires of a few inches long. I don't know upto what frequency a properly built
circuit should operate upto.

I'm also thinking that I am at the limit of the input level that the circuit
can take (although I can't increase the value as it is already the maximum
from the sig gen). Since Vgs quiescent is -2V and Vpgs is -4V I suspect that
Vgs is swinging from -4V to 0V.

My interest in the input range is more relevant for the FET source follower
configuration. This was the one which originally failed due to trying to
buffer to large a voltage swing taken directly from the oscillator tuned
circuit. Again I was having difficulty figuring out just how large a voltage
swing this circuit could buffer.

Any pearls of wisdom would be much appreciated.

I've read all the usual texts but it obviously hasn't quite sunk in!
I've also Googled for relevant information, but I've yet to find a clearly
written explanation that I can understand 100%. Some texts make assumptions or
omit key details.

regards...

--Gary

Gary Morton wrote:
I've been struggling to really understand how FET buffers and simple
FET amplifiers work, since implementing a VCO buffer which didn't
work.

I've recently read the Jan 2005 issue of Practical Wireless in which
there is an article regarding FET amplifiers.

Tonight I selected a 2N3819 FET and made various Vgs vs Id
measurements and plotted them in a table and a graph. I got the
expected curve. Vpgs was around -4V and Idss was 13mA.

I chose an operating point from the table of Id=4.1mA and Vgs=-2V and
from this calculated Rs and chose the nearest standard value of
470ohm.

I then breadboarded (in a 0.1" plug in board) a simple FET amplifier
circuit starting with Rg, Rs, the FET and an input decoupling
capacitor of 1nF only. I used a meter to measure Id. It was 4.3mA -
near enough to the expected value given the choice of the resistor.
The source voltage was 2.0V. All as expected.

I then added Rd. Since Vdd was 10V (from a PSU and decoupled on the
breadboard with 220uF and 0.1uF) I selected 10-((10-2)/2) = 6V for
the drain voltage to allow a symmetrical output voltage swing. Rd was
calculated and a value of 1k was chosen.

Adding this component slightly changed the bias values. I assume that
this is because the Vgs vs Id function changes with Vdd which has
now lowered from the 10V used when the plot was made to the current
value of around 5.7V.

That's correct -- the FET isn't a perfect current source.

I then connected up a signal generator and set the frequency to 9MHz.
For an input swing of 2V pk-to-pk the output voltage was virtually
the same. This is where I have problems understanding exactly what is
happening. I know that since Rs is not decoupled there is negative
feedback and Vgs will vary slightly from the quiescent value. In
doing so Id will change which should be the same as Is which should
modulate the output voltage. I have been trying to visualise how the
operating point is moving on the Vgs vs iD graph, but I am not
getting it.

The presence of the source resistor causes Vgs to change as Id changes,
but in the opposite direction. That is, as Id increases, Vs increases,
causing Vgs to become more negative, which tends to decrease Id. This is
classical negative feedback, which nearly always tends to reduce gain.
The voltage gain should be about Rd / (Rs + 1/gm). Assuming that your
value of gm is correct, 1/gm = 312.5 ohms. This should result in a
voltage gain of about 1.3. Explanations for the difference between this
value and what you saw might be a misestimation of gm, or the shunting
effect of the effective FET drain resistance which is in parallel with
Rd. The effective drain resistance, incidentally, is simply the
reciprocal of the slope of the Id line on the Id vs Vd graph at the
operating point. Sorry, I can't help you with visualizing the operating
point movement on the Id/Vd graph with Rd present.

When I add a decoupling capacitor of 1nF across Rs, I think that I
understand things better. Since the source voltage is now fixed for
RF as the input voltage changes Vgs is directly modulated and
modulates Id. The PW article explains that the gain should be gm *
Rd. Using the table gm should be around 3.2mA/V for the bias values.
Calculations say that the gain should be 0.0032 * 1000 = 3.2, but
using a scope I see a gain of slightly over 2. Even for an input of
2V pk-to-pk the output waveform is pretty good.

Now, Rs is zero as far as the signal is concerned, so your voltage gain
becomes approximately Rd / (1/gm) = gm * Rd. I suspect that your gm
estimation is high. Try also including FET drain resistance to see if
that won't get you closer to the measured value.

Bot notice also that when you're dealing with a large signal, the
variation of gm over the cycle becomes significant. This means that you
have different gain during each part of the signal cycle, resulting in
signal distortion. This will also impact your apparent gain.


I'm puzzled with the discrepancy between measured values and
calculated values. Could the difference in the drain voltage between
making the measurements for the plot and the value used in the
circuit be the reason? I haven't gone back to re-plot the graph.

The circuit gain was consistent from a few MHz upto around 15MHz when
it dropped of considerably. Not bad for a breadboarded design
connected with wires of a few inches long. I don't know upto what
frequency a properly built circuit should operate upto.

FET amplifiers work well into the VHF and even UHF range, but with lower
values of resistance and different topologies such as common base.
Device capacitance, both fundamental and multiplied by Miller effect,
become limiting factors, as do case parasitics.

I'm also thinking that I am at the limit of the input level that the
circuit can take (although I can't increase the value as it is
already the maximum from the sig gen). Since Vgs quiescent is -2V and
Vpgs is -4V I suspect that Vgs is swinging from -4V to 0V.

That's hard to say, since pinchoff voltage isn't a hard limit. In fact,
I suspect that it's more like -8 to -10 volts for your device, as
typically measured at 0.1 or 1 nA Id. But the distortion will get worse
and worse and begin looking like a soft clipping at some point.


My interest in the input range is more relevant for the FET source
follower configuration. This was the one which originally failed due
to trying to buffer to large a voltage swing taken directly from the
oscillator tuned circuit. Again I was having difficulty figuring out
just how large a voltage swing this circuit could buffer.

Source followers have an output resistance of around 1/gm, which is
typically in the range of a few hundred ohms for small signal JFETs.
This is very high compared to a bipolar transistor, and so a source
follower will badly attenuate a signal delivered to, say, a 50 ohm load,
unless a transformer is used so the source follower sees a higher load
impedance. They're suitable only for a limited number of applications,
and not nearly so generally useful as a bipolar emitter follower.

Any pearls of wisdom would be much appreciated.

You're doing a great job of learning about how these devices work --
keep it up. Load line analysis can be a great tool, as you've found, to
visualize how the various voltages and currents interact. But you have
to be aware that there can be a very great difference between one
individual device and another, even with the same part number -- for
example, a 10:1 range of possible Idss isn't unusual. So the curves you
get from one device may be very different from ones you get from the
next one you pick from the drawer. This makes it a real challenge to
design circuits with FETs which can be duplicated. There's no problem
designing a circuit to work with a particular, individual device, but
don't expect someone else to build the same circuit and get the same
results. It can, of course, be done, for certain types of circuits,
often using considerable feedback and sacrificing gain for
repeatability. But it does take a pretty deep understanding of the
interrelationship among the parameters. And you're on your way to
getting that.

I've read all the usual texts but it obviously hasn't quite sunk in!
I've also Googled for relevant information, but I've yet to find a
clearly written explanation that I can understand 100%. Some texts
make assumptions or omit key details.

For the level of understanding you're looking for, I'd avoid the
technician-level books and get some textbooks written for electronics
courses in an Electrical Engineering curriculum. Mine are awfully dated,
but I'm sure there are plenty of newer ones available. I also suggest
that you get a copy of SPICE and learn to use it. It'll allow you to
poke around in a circuit where your 'scope can't go, to get a better
understanding of what's happening. You can also do such things as build
a transistor model piece by piece to see what effect each part has --
you'll be surprised how well a very simple model can often work. And
finally, you can see how much harm your long leads and other layout
techniques might or might not be having on the results. It's a terrific
learning tool.

Roy Lewallen, W7EL

Roy,

many thanks for taking the time to compose such a detailed reply.

I continued to experiment and make some more measurements, but I got
sidetracked into finally constructing a simple SSB receiver. I then got side
tracked into trying to figure out why the radio doesn't work very well. Even
the damn 2N3819 FET oscillator didn't work! I even tried different FETs. That
was fixed by adding extra source resistance.

The following table may not look right as it appears to have tabs in it.

vga in V
idd in mA
gm in ms
Rs in ohm
Rdrain
0.0 13.2 n/a 0.0 n/a
-0.2 12.1 5.1 17.6 196.35
-0.5 10.5 4.8 51.3 207.54
-0.7 9.6 4.4 77.0 227.01
-1.2 7.8 4.3 149.7 231.31
-1.5 6.4 4.2 227.1 240.46
-1.8 5.1 3.8 348.9 260.87
-2.1 4.1 3.5 498.8 284.05 - operating point
-2.5 2.6 3.2 984.4 312.25
-2.9 1.6 2.5 1781.3 398.94
-3.3 0.7 1.8 4808.8 541.10
-3.6 0.1 n/a 26000.0 n/a

I'd never heard of the effect of "effective drain resistance". I can't recall
seeing it explained in any of the texts which I have read. Mind you the PW
article suggested that the graph of Id vs Vgs was a straight line for smaller
values of Vgs! I re-calculated Rd using this extra value but I just got a less
than unity amplifier.

It seems to me and you seem to back this up the a FET buffer whilst a useful
impedance converter also distorts the signal due to the x squared function.
This makes it good for mixers though. I do often see FETs used as buffers for
VFOs in simple rx designs.

Anyway I'll do some more experimenting until I get theory and practice to match.

BTW I have already played with Spice, using it to plot various curves (Vd vs
Id for various Vgs, and Id vs Vgs). I have also simulated FET amplifiers and
buffers. Now I need to change the 2N3819 model to match the "slope" of my FET
and see what the simulator gives.

regards...

--Gary