JLB wrote:
Typically the DDS is used as the reference oscillator for the PLL, resulting
in the VCO being at a multiple of the DDS output frequency. The idea being
that the VCO output will have decent phase noise performance with the fine
frequency resolution of the DDS, and resaonably fast stepping times---"the
best of both worlds", you might say.

I discovered an interesting alternative at :
http://lea.hamradio.si/~s57nan/ham_r.../dds_9851.html



This idea has the DDS acting as a programmable divider inside the PLL
feedback loop. Ok, what are the advantages or disadvantages of doing this?
What does it do to the phase noise and lock-up time? And what about the
spurs?



Jim

N8EE


There are several ways to combine the dds and pll.
If you do it this way, by using the dds as the divider in a pll circuit
your dds must accept the clock rate of the pll output frequency. DDS
circuits that operate at clock rates as high as 400mhz are now common.
The software to calculate the divisor constant for the dds given the
desired pll output frequency might involve floating point math, I briefly
looked at it and didn't see a clear way to do it with integers using an
8051.

Another circuit uses the dds to provide the reference (R) for the phase
comparater of the PLL and setting the output frequency is now a matter of
selecting the PLL divisor ratio and the reference frequency. The DDS
provides
the fine tuning, and the PLL the course adjustment. I worked up a
design where
the reference for the PLL was nominally around 100khz (actually 64 or 128khz
so it would be an even power of two). Then the software was an integer math
problem, though it did require either integer multiplication or
division. I was
able to invert the problem so only integer multiplication was required, and
a table driven routine will work fine on the 8051. In fact, I was able
to insert the
IF offset into the tables, and all the routines are in binary, NOT BCD.
A binary
to bcd conversion is required to display the frequency, and bcd to binary is
needed for keypad entry, but the rotary shaft encoder could drive in binary.

If anyone has build a radio using a dds/pll vfo, I'd like to know how
they handled
the user interface in software, which micros they used and how they
handled the
math to calculate the divisor constants.