In article , "W3JDR"
writes:

The important factors for my applications are good tuning resolution,
reasonable lock-up time, and minimal phase noise. Of course, defining 'how
good is good enough' is somewhat subjective. Whether it's done as a PLL or
an FLL is somewhat semantic as most PLL synthesizer's really don't control
the short-term phase real well anyway.

Short-term phase stability almost always lies in the VCO design with
some disturbance possible by an incorrect loop filter. That has little
to do whether the VCO is used with a PLL or DDS.

To be phase-stable (i.e., reduce short-term jitter), the VCO supply rails
should be bypassed adequately well up into the RF range of the VCO
and the control voltage line absolutely free from any loop-induced
pickup almost to the VCO's RF range. Iron powder or ferrite beads,
even slabs of the stuff, can halp on the control line. Stability also
involves using whatever active device in the oscillator at its optimum
lowest-noise point...that's device dependent and not all manufacturers
supply such data.

In truth, I've never had experience with the PLL or DDS dividers as an
integral part of the frequency control determining processor. I've always
had to work some to make the external-divider kind lay down and be
nice. I would imagine there's more fun and games with a combined
type using a Microchip processor being both controller and divider. :-)

Len Anderson
retired (from regular hours) electronic engineer person