Frequency Division
 

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W) wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.

Both of the above may provide acceptable jitter.

3. a no-VCO approach - frequency double twice using XOR gates, then divide by
five and finally by two in say a 7490. Simple glue logic chips.

4. use a micro.

I would certainly expect both 3 & 4 to present more jitter than well-implemented
VCO solutions. If jitter is critical to the application, this needs to be
indicated.

On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W) wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.

Both of the above may provide acceptable jitter.

3. a no-VCO approach - frequency double twice using XOR gates, then divide by
five and finally by two in say a 7490. Simple glue logic chips.

4. use a micro.

I would certainly expect both 3 & 4 to present more jitter than well-implemented
VCO solutions. If jitter is critical to the application, this needs to be
indicated.

Take a look at Analog Devices' line of DDS chips. Pretty much a one-chip
(needs ucontroller to drive it) digital solution to turn your 10MHz clock
into virtually any frequency below 5 MHz (in theory; below 4MHz in easy
practicality). The AD9834 only consumes 20mw at 3.3 VDC. There are many
other devices in the product line. Many have built-in comparators to produce
square-wave output.

Joe
W3JDR


"Mike W" wrote in message
...
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

Take a look at Analog Devices' line of DDS chips. Pretty much a one-chip
(needs ucontroller to drive it) digital solution to turn your 10MHz clock
into virtually any frequency below 5 MHz (in theory; below 4MHz in easy
practicality). The AD9834 only consumes 20mw at 3.3 VDC. There are many
other devices in the product line. Many have built-in comparators to produce
square-wave output.

Joe
W3JDR


"Mike W" wrote in message
...
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

"budgie" wrote in message
...
On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W)
wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all
provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg
source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.


I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap
to alter the VXO frequency (or use an ordinary diode or LED as the varicap,
see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent
stability of the VXO will allow you to use a very slow PLL, which will
result in minimal jitter.

Hans G0UPL
http://www.HansSummers.com

"budgie" wrote in message
...
On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W)
wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all
provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg
source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.


I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap
to alter the VXO frequency (or use an ordinary diode or LED as the varicap,
see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent
stability of the VXO will allow you to use a very slow PLL, which will
result in minimal jitter.

Hans G0UPL
http://www.HansSummers.com

Multiply by four, then divide by five and by two. Or divide by five,
then multiply by four and divide by two. For the best symmetry, you
should expect to use a divide-by-two in the last stage, though you can
get close to 50% with triggering off both rising and falling edges.
There are other possible trick ways but the mpy/div are
straightforward. You could, for example, divide the ref by five and a
4MHz VCO by two and build a PLL to control the 4MHz VCO.

Cheers,
Tom

(Mike W) wrote in message ...
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

Multiply by four, then divide by five and by two. Or divide by five,
then multiply by four and divide by two. For the best symmetry, you
should expect to use a divide-by-two in the last stage, though you can
get close to 50% with triggering off both rising and falling edges.
There are other possible trick ways but the mpy/div are
straightforward. You could, for example, divide the ref by five and a
4MHz VCO by two and build a PLL to control the 4MHz VCO.

Cheers,
Tom

(Mike W) wrote in message ...
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

In article ,
(Mike W) writes:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

A more direct way, with very little jitter, is to double the 10 MHz
reference with a dual diode arrangment, output tuned to 20 MHz,
then into amplification (if needed), through a Schmitt inverter,
another (!) dual diode doubler with output tuned to 40 MHz. Again
amplification (if needed) and another Schmitt inverter to square
up the 40 MHz. Divide the 40 MHz by 10 in a Johnson counter to
achieve the 50% duty cycle. Broad tuning, no real problems there.
Very direct. Minimal jitter.

Johnson counters aren't common but they aren't made from
unobtainium either. The CD4017 is an example and still available
although it isn't fast enough for this application. Dividing by 10 via
a Johnson counter needs a 5-stage shift register arrangement
which can be done from 74LS or 74F or 74AC components (a
4-bit SR IC plus a flip-flop to complete the 5 stages).

If operating at slower rates, the 50% duty cycle would appear at
the "Carry Out" pin of a CD4017.

A good simple explanation of Johnson counters is at:

http://www.play-hookey.com/digital/johnson_counter.html

Some other suggestions might suggest themselves if you explain
the "timebase" in more detail.

Len Anderson
retired (from regular hours) electronic engineer person