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#1
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Frequency Division
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. atb Mikw |
#2
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#3
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#4
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Take a look at Analog Devices' line of DDS chips. Pretty much a one-chip
(needs ucontroller to drive it) digital solution to turn your 10MHz clock into virtually any frequency below 5 MHz (in theory; below 4MHz in easy practicality). The AD9834 only consumes 20mw at 3.3 VDC. There are many other devices in the product line. Many have built-in comparators to produce square-wave output. Joe W3JDR "Mike W" wrote in message ... I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. atb Mikw |
#5
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Take a look at Analog Devices' line of DDS chips. Pretty much a one-chip
(needs ucontroller to drive it) digital solution to turn your 10MHz clock into virtually any frequency below 5 MHz (in theory; below 4MHz in easy practicality). The AD9834 only consumes 20mw at 3.3 VDC. There are many other devices in the product line. Many have built-in comparators to produce square-wave output. Joe W3JDR "Mike W" wrote in message ... I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. atb Mikw |
#6
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"budgie" wrote in message ... On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W) wrote: I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. Several approaches spring to mind. You stated "accurate" - they all provide that, but jitter is introduced in all of them: 1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg source divided by ten. 2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and divided down (by in this case 10) to give 4 MHz output. I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap to alter the VXO frequency (or use an ordinary diode or LED as the varicap, see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent stability of the VXO will allow you to use a very slow PLL, which will result in minimal jitter. Hans G0UPL http://www.HansSummers.com |
#7
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"budgie" wrote in message ... On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W) wrote: I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. Several approaches spring to mind. You stated "accurate" - they all provide that, but jitter is introduced in all of them: 1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg source divided by ten. 2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and divided down (by in this case 10) to give 4 MHz output. I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap to alter the VXO frequency (or use an ordinary diode or LED as the varicap, see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent stability of the VXO will allow you to use a very slow PLL, which will result in minimal jitter. Hans G0UPL http://www.HansSummers.com |
#8
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Multiply by four, then divide by five and by two. Or divide by five,
then multiply by four and divide by two. For the best symmetry, you should expect to use a divide-by-two in the last stage, though you can get close to 50% with triggering off both rising and falling edges. There are other possible trick ways but the mpy/div are straightforward. You could, for example, divide the ref by five and a 4MHz VCO by two and build a PLL to control the 4MHz VCO. Cheers, Tom (Mike W) wrote in message ... I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. atb Mikw |
#9
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Multiply by four, then divide by five and by two. Or divide by five,
then multiply by four and divide by two. For the best symmetry, you should expect to use a divide-by-two in the last stage, though you can get close to 50% with triggering off both rising and falling edges. There are other possible trick ways but the mpy/div are straightforward. You could, for example, divide the ref by five and a 4MHz VCO by two and build a PLL to control the 4MHz VCO. Cheers, Tom (Mike W) wrote in message ... I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave to use as a timebase. I have a 10Mhz IQD frequency standard of suitable accuracy. How can I divide this to produce the 50% duty cycle 4Mhz signal?. Is it even possible with logic alone?. I can see how to mix with either 6Mhz or 14Mhz, but this then detracts from the required accuracy. atb Mikw |
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