Paul Burridge wrote in message . ..
Hi all,

Is there some black magic required to get higher order harmonics out
of an oscillator?
I'm only trying to get 17.2Mhz out of a 3.44Mhz source and am thus far
failing spectacularly. I've tried everything I can think of so far to
no avail. All I can get apart from the fundamental is a strong third
harmonic on 10.32Mhz, regardless of what I tune for. I've tried
passing the osc output through two successive inverter gates to
sharpen it up, but still nothing beyond the third appears after tuned
amplification for the fifth. I no longer have a spectrum analyser so
can't check for the presence of a decent comb of harmonics at the
input to the multiplier stage but can only assume the fifth is well
down in the mush for some reason.

Fifth harmonic frequency multipliers do exist, but it's usually much
easier to double and triple your way to the final frequency if possible.
(You just discovered this, I think!)

The lack of even harmonics is typical of push-pull stages ... if you
are messing around with CMOS gates, you might try using a TTL gate
(which pulls low much stronger than it pulls high) or an open collector
TTL gate, both with smmallish (100-200 ohm) pull-up resistors for
doubling.

Why not do a x3 followed by a x2 to get 17.2 MHz out of 2.866 MHz?

Tim.

On 13 Mar 2004 07:33:15 -0800, (Tim Shoppa)
wrote:

Fifth harmonic frequency multipliers do exist, but it's usually much
easier to double and triple your way to the final frequency if possible.
(You just discovered this, I think!)

Yeah, but trying to get the 5th is hardly asking for the moon...

The lack of even harmonics is typical of push-pull stages ... if you
are messing around with CMOS gates, you might try using a TTL gate
(which pulls low much stronger than it pulls high) or an open collector
TTL gate, both with smmallish (100-200 ohm) pull-up resistors for
doubling.

I've a reasonably fast Schmitt I'm going to stick in there in place of
the 74HC04 before I resort to anything fancy (same pin-out).

Why not do a x3 followed by a x2 to get 17.2 MHz out of 2.866 MHz?

Because I don't have a rock lying about for that fundamental!

Hopefully some supreme being here will spot a problem with the traces
I've now posted...
--

The BBC: Licensed at public expense to spread lies.

In article , Paul Burridge
writes:

On 13 Mar 2004 07:33:15 -0800, (Tim Shoppa)
wrote:

Fifth harmonic frequency multipliers do exist, but it's usually much
easier to double and triple your way to the final frequency if possible.
(You just discovered this, I think!)

Yeah, but trying to get the 5th is hardly asking for the moon...

In a way, it IS. Fifth harmonic of an infinitely sharp transition
rectangular waveform is still low in energy compared to the
fundamental. Chances are that a single stage using an active
device as a quintupler will NOT be successful, transistor or tube
(valve).

Let's get to some specifics on this problem -

1. Let us know what you are using to determine whether or not
a 5th harmonic exists. The lack of indication may be due to
whatever it is (not a spectrum analyzer) being used.
2. Describe the multiplier stage in more detail and include an
approximate level and impedance/admittance of the RF
source. That would include supply rails and biasing.
3. Describe whatever is being used to select the 5th harmonic
and inhibit the fundamental and other harmonics. There's
lots of energy at many different frequencies floating around
there and you only want one frequency.
4. Review again with us the output drive level requirements so
we can get a handle on that.
5. If you are using an oscilloscope to measure the fundamental
waveform, estimate the actual risetime/falltime based on the
rise/fall times limits of the oscilloscope. That yields some
basic data that can be applied to a Fourier series to determine
the level of 5th harmonic energy you have to work with. [that
will also reveal the approximate frequency limits of the scope]

The lack of even harmonics is typical of push-pull stages ... if you
are messing around with CMOS gates, you might try using a TTL gate
(which pulls low much stronger than it pulls high) or an open collector
TTL gate, both with smmallish (100-200 ohm) pull-up resistors for
doubling.

I've a reasonably fast Schmitt I'm going to stick in there in place of
the 74HC04 before I resort to anything fancy (same pin-out).

Why not do a x3 followed by a x2 to get 17.2 MHz out of 2.866 MHz?

Because I don't have a rock lying about for that fundamental!

Hint: A mixed 2x and 3x = 5x out if filtered to pass that. No lying-
around rock needed. [not an optimum solution]

Note: As already pointed out, a single PLL IC can do the job in the
same PCB footprint.

When frustration hits a peak, it's time to sit back away from the
problem and do an objective review of what is the overall task and
what you've accomplished so far and what you know about certain
circuits fundamentals. General problem descriptions only result in
general solutions without quantitative values needed for a specific
application.

I've found that NON-linear circuits (a multiplier stage is definietly
in the non-linear category) take rather more development time
than a linear circuit. There's lots of different things going on in a
multiplier circuit and those have to be considered for the whole.

Hopefully some supreme being here will spot a problem with the traces
I've now posted...

Try as we might in the depths of our frustrations, supreme beings
tend not to intervene in us humans' petty affairs. :-)

Len Anderson
retired (from regular hours) electronic engineer person

On 13 Mar 2004 19:00:19 GMT, (Avery Fineman)
wrote:

In a way, it IS. Fifth harmonic of an infinitely sharp transition
rectangular waveform is still low in energy compared to the
fundamental. Chances are that a single stage using an active
device as a quintupler will NOT be successful, transistor or tube
(valve).

I find that surprising but bow to your superior knowledge...

Let's get to some specifics on this problem -

1. Let us know what you are using to determine whether or not
a 5th harmonic exists. The lack of indication may be due to
whatever it is (not a spectrum analyzer) being used.

As I said, since I've disposed of my SA I have no way of detecting the
presence of the 5th unless it's strong enough to be seen by 'scope or
read by my frequency counter. (Except for your brilliant idea of using
an HF rx, that is, which I intend to implement 2morrow).

2. Describe the multiplier stage in more detail and include an
approximate level and impedance/admittance of the RF
source. That would include supply rails and biasing.

There's a circuit diagram now viewable on abse under a similar thread
title. That should answer all your queries...

3. Describe whatever is being used to select the 5th harmonic
and inhibit the fundamental and other harmonics. There's
lots of energy at many different frequencies floating around
there and you only want one frequency.

Nothing more than what you can see in the schematic's two stages.

4. Review again with us the output drive level requirements so
we can get a handle on that.

It's got to eventually end up feeding another CMOS inverter for a
tripler stage.

5. If you are using an oscilloscope to measure the fundamental
waveform, estimate the actual risetime/falltime based on the
rise/fall times limits of the oscilloscope. That yields some
basic data that can be applied to a Fourier series to determine
the level of 5th harmonic energy you have to work with. [that
will also reveal the approximate frequency limits of the scope]

I prefer to go by the device's datasheet. In this case, the r/f times
are 7 to 8nS.

If there's anything I've missed out, lemme know...

--

The BBC: Licensed at public expense to spread lies.

On 13 Mar 2004 19:00:19 GMT, (Avery Fineman)
wrote:

In a way, it IS. Fifth harmonic of an infinitely sharp transition
rectangular waveform is still low in energy compared to the
fundamental. Chances are that a single stage using an active
device as a quintupler will NOT be successful, transistor or tube
(valve).

I find that surprising but bow to your superior knowledge...

Let's get to some specifics on this problem -

1. Let us know what you are using to determine whether or not
a 5th harmonic exists. The lack of indication may be due to
whatever it is (not a spectrum analyzer) being used.

As I said, since I've disposed of my SA I have no way of detecting the
presence of the 5th unless it's strong enough to be seen by 'scope or
read by my frequency counter. (Except for your brilliant idea of using
an HF rx, that is, which I intend to implement 2morrow).

2. Describe the multiplier stage in more detail and include an
approximate level and impedance/admittance of the RF
source. That would include supply rails and biasing.

There's a circuit diagram now viewable on abse under a similar thread
title. That should answer all your queries...

3. Describe whatever is being used to select the 5th harmonic
and inhibit the fundamental and other harmonics. There's
lots of energy at many different frequencies floating around
there and you only want one frequency.

Nothing more than what you can see in the schematic's two stages.

4. Review again with us the output drive level requirements so
we can get a handle on that.

It's got to eventually end up feeding another CMOS inverter for a
tripler stage.

5. If you are using an oscilloscope to measure the fundamental
waveform, estimate the actual risetime/falltime based on the
rise/fall times limits of the oscilloscope. That yields some
basic data that can be applied to a Fourier series to determine
the level of 5th harmonic energy you have to work with. [that
will also reveal the approximate frequency limits of the scope]

I prefer to go by the device's datasheet. In this case, the r/f times
are 7 to 8nS.

If there's anything I've missed out, lemme know...

--

The BBC: Licensed at public expense to spread lies.

On Sat, 13 Mar 2004 16:51:48 +0000, Paul Burridge wrote:

On 13 Mar 2004 07:33:15 -0800, (Tim Shoppa)
wrote:

Fifth harmonic frequency multipliers do exist, but it's usually much
easier to double and triple your way to the final frequency if possible.
(You just discovered this, I think!)

Yeah, but trying to get the 5th is hardly asking for the moon...

The lack of even harmonics is typical of push-pull stages ... if you
are messing around with CMOS gates, you might try using a TTL gate
(which pulls low much stronger than it pulls high) or an open collector
TTL gate, both with smmallish (100-200 ohm) pull-up resistors for
doubling.

I've a reasonably fast Schmitt I'm going to stick in there in place of
the 74HC04 before I resort to anything fancy (same pin-out).

Why not do a x3 followed by a x2 to get 17.2 MHz out of 2.866 MHz?

Because I don't have a rock lying about for that fundamental!

Hopefully some supreme being here will spot a problem with the traces
I've now posted...

Just a rough guess, since your calling on supreme beings...

That input cap... I take it the input source is a reasonable
estimate of your square wave... if the time constant of that input
RC net isn't right, it'll be a differentiator, and turn your square
wave into pulses coincident with the rising and falling edges. Your
scope trace suggested otherwise, but IIRC, at that tin=me you were
using the filter at the input to the mult., xo things have changed.

It doesn't look like you're biased in Class C. All the mults I've
seen are Class C biased with the tuned circuit on the collector. And
remember, when you're doing this later for some other purpose, in
Class C, the transistors Vceo - reverse breakdown - must be at least
twice the supply voltage.

--
Best Regards,
Mike

On Sat, 13 Mar 2004 20:23:45 -0500, Active8
wrote:

Just a rough guess, since your calling on supreme beings...

The post is still vacant as yet...
:-)

That input cap... I take it the input source is a reasonable
estimate of your square wave... if the time constant of that input
RC net isn't right, it'll be a differentiator, and turn your square
wave into pulses coincident with the rising and falling edges. Your
scope trace suggested otherwise, but IIRC, at that tin=me you were
using the filter at the input to the mult., xo things have changed.

There's been no filtering (other than the selective properties of the
tank circuits) whatsoever employed thus far.

It doesn't look like you're biased in Class C. All the mults I've
seen are Class C biased with the tuned circuit on the collector. And
remember, when you're doing this later for some other purpose, in
Class C, the transistors Vceo - reverse breakdown - must be at least
twice the supply voltage.

Yup, perfectly correct. I must admit that going the class C route with
the tank tuned to the required harmonic was the way I was 'brought up'
as it were. Class C typically generates lots of harmonics as you
obviously know. This multiplier seems to be operating in class A,
which I admit is odd given its high linearity. But I didn't design the
multiplying stage you see here, but the guy who did is an RF expert so
I don't argue. :-)

But you've just given me an idea: maybe I should increase the value of
the 82 ohm base-ground resistor to increase drive signal level and tip
the stage into class C. Worth a try?

--

The BBC: Licensed at public expense to spread lies.

On Sun, 14 Mar 2004 13:14:40 +0000, Paul Burridge wrote:

On Sat, 13 Mar 2004 20:23:45 -0500, Active8
wrote:

Just a rough guess, since your calling on supreme beings...

The post is still vacant as yet...
:-)

That input cap... I take it the input source is a reasonable
estimate of your square wave... if the time constant of that input
RC net isn't right, it'll be a differentiator, and turn your square
wave into pulses coincident with the rising and falling edges. Your
scope trace suggested otherwise, but IIRC, at that tin=me you were
using the filter at the input to the mult., xo things have changed.

There's been no filtering (other than the selective properties of the
tank circuits) whatsoever employed thus far.

It doesn't look like you're biased in Class C. All the mults I've
seen are Class C biased with the tuned circuit on the collector. And
remember, when you're doing this later for some other purpose, in
Class C, the transistors Vceo - reverse breakdown - must be at least
twice the supply voltage.

Yup, perfectly correct. I must admit that going the class C route with
the tank tuned to the required harmonic was the way I was 'brought up'
as it were. Class C typically generates lots of harmonics as you
obviously know. This multiplier seems to be operating in class A,
which I admit is odd given its high linearity. But I didn't design the
multiplying stage you see here, but the guy who did is an RF expert so
I don't argue. :-)

But you've just given me an idea: maybe I should increase the value of
the 82 ohm base-ground resistor to increase drive signal level and tip
the stage into class C. Worth a try?

Nah. With a *sine* input, you'd bias it so it only conducts for less
than 180 degrees of the fundamental's cycle - keep the trans *out*
of conduction for the most part. Now that I think of it, yer using a
square wave and should have the stinkin' harmonic already, duh. What
was I thinkin'? I still wonder what that input cap is doing to the
edges. The trace you posted indicates it *might* be ok if nothing
changed.

Just for grins, get rid of that input cap and do whatever with the
bias to allow you to DC couple the multiplier. That's pretty class
C'ish assuming a 0 - 5V square wave. Don't fry your b-e junction.
Something's wiping out your 5th, so lets get that input RC outta
there.
--
Best Regards,
Mike

On Sun, 14 Mar 2004 15:55:04 -0500, Active8
wrote:

On Sun, 14 Mar 2004 13:14:40 +0000, Paul Burridge wrote:

On Sat, 13 Mar 2004 20:23:45 -0500, Active8
wrote:

Just a rough guess, since your calling on supreme beings...

The post is still vacant as yet...
:-)

That input cap... I take it the input source is a reasonable
estimate of your square wave... if the time constant of that input
RC net isn't right, it'll be a differentiator, and turn your square
wave into pulses coincident with the rising and falling edges. Your
scope trace suggested otherwise, but IIRC, at that tin=me you were
using the filter at the input to the mult., xo things have changed.

There's been no filtering (other than the selective properties of the
tank circuits) whatsoever employed thus far.

It doesn't look like you're biased in Class C. All the mults I've
seen are Class C biased with the tuned circuit on the collector. And
remember, when you're doing this later for some other purpose, in
Class C, the transistors Vceo - reverse breakdown - must be at least
twice the supply voltage.

Yup, perfectly correct. I must admit that going the class C route with
the tank tuned to the required harmonic was the way I was 'brought up'
as it were. Class C typically generates lots of harmonics as you
obviously know. This multiplier seems to be operating in class A,
which I admit is odd given its high linearity. But I didn't design the
multiplying stage you see here, but the guy who did is an RF expert so
I don't argue. :-)

But you've just given me an idea: maybe I should increase the value of
the 82 ohm base-ground resistor to increase drive signal level and tip
the stage into class C. Worth a try?

Nah. With a *sine* input, you'd bias it so it only conducts for less
than 180 degrees of the fundamental's cycle - keep the trans *out*
of conduction for the most part. Now that I think of it, yer using a
square wave and should have the stinkin' harmonic already, duh. What
was I thinkin'? I still wonder what that input cap is doing to the
edges. The trace you posted indicates it *might* be ok if nothing
changed.

Just for grins, get rid of that input cap and do whatever with the
bias to allow you to DC couple the multiplier. That's pretty class
C'ish assuming a 0 - 5V square wave. Don't fry your b-e junction.
Something's wiping out your 5th, so lets get that input RC outta
there.

Hi Mike,
I'm made your suggested changes and re-run the sim.
The new output result across the 1k resistor is now viewable on
abse....

--

The BBC: Licensed at public expense to spread lies.

On Sun, 14 Mar 2004 15:55:04 -0500, Active8
wrote:

On Sun, 14 Mar 2004 13:14:40 +0000, Paul Burridge wrote:

On Sat, 13 Mar 2004 20:23:45 -0500, Active8
wrote:

Just a rough guess, since your calling on supreme beings...

The post is still vacant as yet...
:-)

That input cap... I take it the input source is a reasonable
estimate of your square wave... if the time constant of that input
RC net isn't right, it'll be a differentiator, and turn your square
wave into pulses coincident with the rising and falling edges. Your
scope trace suggested otherwise, but IIRC, at that tin=me you were
using the filter at the input to the mult., xo things have changed.

There's been no filtering (other than the selective properties of the
tank circuits) whatsoever employed thus far.

It doesn't look like you're biased in Class C. All the mults I've
seen are Class C biased with the tuned circuit on the collector. And
remember, when you're doing this later for some other purpose, in
Class C, the transistors Vceo - reverse breakdown - must be at least
twice the supply voltage.

Yup, perfectly correct. I must admit that going the class C route with
the tank tuned to the required harmonic was the way I was 'brought up'
as it were. Class C typically generates lots of harmonics as you
obviously know. This multiplier seems to be operating in class A,
which I admit is odd given its high linearity. But I didn't design the
multiplying stage you see here, but the guy who did is an RF expert so
I don't argue. :-)

But you've just given me an idea: maybe I should increase the value of
the 82 ohm base-ground resistor to increase drive signal level and tip
the stage into class C. Worth a try?

Nah. With a *sine* input, you'd bias it so it only conducts for less
than 180 degrees of the fundamental's cycle - keep the trans *out*
of conduction for the most part. Now that I think of it, yer using a
square wave and should have the stinkin' harmonic already, duh. What
was I thinkin'? I still wonder what that input cap is doing to the
edges. The trace you posted indicates it *might* be ok if nothing
changed.

Just for grins, get rid of that input cap and do whatever with the
bias to allow you to DC couple the multiplier. That's pretty class
C'ish assuming a 0 - 5V square wave. Don't fry your b-e junction.
Something's wiping out your 5th, so lets get that input RC outta
there.

Hi Mike,
I'm made your suggested changes and re-run the sim.
The new output result across the 1k resistor is now viewable on
abse....

--

The BBC: Licensed at public expense to spread lies.