On Monday, June 9, 2003 at 9:58:46 AM UTC+10, John Miles wrote:
This question may be related to one that Jan Wagner posted awhile back.
Jan was having trouble with excessive jitter

PLL-like nature of these graphs suggested a problem with the chip's
clock multiplier. I was able to confirm that indeed, the problem
occurred ONLY with the DDS chip's internal PLL-based clock multiplier
engaged, with a 10 MHz external clock being multiplied to frequencies
between 80 and 120 MHz. With an unmultiplied 100 MHz external clock,
the DDS works perfectly with no 'ears', spurs, or instability.

At this time I don't understand what's going on with this assembly.
It's not a complicated circuit; the AD9854 is a very robust, hard-to-
screw-up chip, and in general there's very little to go wrong. I have a
good deal of experience with the AD9852 / AD9854 parts, and have never
seen this behavior before.

Has anyone else run into this weirdness?

-- jm

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JIM .. phase jitter in this device is certainly due to the clk multiplier, what did u do to pin 22 , spec is to decouple it to Analog Ground , bet u couple it to Dig GND . U also need 2 regulated supplies not the lazy single u have. not only that 10MHz clock is outside the spec of min 20MHz .. Regardless, of those 2 or 3 failures , a 4:1 balun ought be used for ext single to differential input for such a critical issue.

Little wonder amateur radio is called by the name. Go on.. get out of joint

I was searching for issues in the Chinese boards.. have bought the parallel port with mezzanine controller and the only USB single board with JTAG and dual regulators .. Anyone used either of these $100 boards ? its 2016 , sure is hard to find peop outside of China AD using the good oil .. this is actually a great digital PLL for a Rx digital radio ..Rus Talisin on g+