Everyone please read the 11C44 datasheet at:

http://ira.club.atnet.at/rd/11c44/11C44.html

before declaring there is no dead zone. See figure 11.

Rick N6RK

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

Hello All

Rick Karlquist. N6RK, on 5/28/04 wrote:
Everyone please read the 11C44 datasheet at:

http://ira.club.atnet.at/rd/11c44/11C44.html

before declaring there is no dead zone. See figure 11.

Rick N6RK

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
SNIP

See also 'The PLL Dead Zone and How to Avoid it', A. Hill & J. Surber, RF
Design, March 1992, pp131-134. The authors were with Analog Devices and
compared the performance of the AD9901 with that of the MC4044.

My understanding of the AD9901 is that it behaves as a edge controlled
frequency detector, until it gets close enough in frequency, when it switches
to being an EXOR phase detector.

I am struggling to understand the comment above that the AD9901 is not suitable
for use in frequency synthesisers because of the large spurious sidebands
arising from its use. What causes the additional sidebands ?

Elsewhere in this thread there seems to have been some debate on the operation
of the phase frequency detector. IMHO if the phase detector has a tri-state
output then the loop over time must lock with no phase difference between the
reference and controlled signals, ie 0 degrees.

73 John KC0GGH

John,

Elsewhere in this thread there seems to have been some debate on the
operation
of the phase frequency detector. IMHO if the phase detector has a
tri-state
output then the loop over time must lock with no phase difference between
the
reference and controlled signals, ie 0 degrees.

Theoretically, the edge controlled PFD locks the signal & reference with 0
degrees phase error. When the loop is locked, the output pulses from the PFD
are theoretically infinitesimally small. However, neither the PFD chip nor
the external charge pump/loop filter are perfect. Any leakage in the charge
pump and/or loop filter causes the PFD to continually output wider than
normal pulses in order to supply the additional charge current necessary to
make up for the current leakage. This results in a non-zero phase error at
the PFD inputs.

I am struggling to understand the comment above that the AD9901 is not
suitable
for use in frequency synthesizers because of the large spurious sidebands
arising from its use. What causes the additional sidebands ?

As mentioned, the PFD output pulses approach zero width at lock, making it
easier to filter the pulses down to pure DC in the charge pump/loop filter.
The XOR PD will output a 50% duty cycle pulse train at lock. This is much
more difficult to filter down to pure DC, resulting in modulation of the
VCO, and thus sidebands.

Joe
W3JDR



"John Crabtree" wrote in message
...
Hello All

Rick Karlquist. N6RK, on 5/28/04 wrote:
Everyone please read the 11C44 datasheet at:

http://ira.club.atnet.at/rd/11c44/11C44.html

before declaring there is no dead zone. See figure 11.

Rick N6RK

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
SNIP

See also 'The PLL Dead Zone and How to Avoid it', A. Hill & J. Surber, RF
Design, March 1992, pp131-134. The authors were with Analog Devices and
compared the performance of the AD9901 with that of the MC4044.

My understanding of the AD9901 is that it behaves as a edge controlled
frequency detector, until it gets close enough in frequency, when it
switches
to being an EXOR phase detector.

I am struggling to understand the comment above that the AD9901 is not
suitable
for use in frequency synthesisers because of the large spurious sidebands
arising from its use. What causes the additional sidebands ?

Elsewhere in this thread there seems to have been some debate on the
operation
of the phase frequency detector. IMHO if the phase detector has a
tri-state
output then the loop over time must lock with no phase difference between
the
reference and controlled signals, ie 0 degrees.

73 John KC0GGH

In article , "W3JDR"
writes:

John,

Elsewhere in this thread there seems to have been some debate on the
operation
of the phase frequency detector. IMHO if the phase detector has a
tri-state
output then the loop over time must lock with no phase difference between
the
reference and controlled signals, ie 0 degrees.

Theoretically, the edge controlled PFD locks the signal & reference with 0
degrees phase error. When the loop is locked, the output pulses from the PFD
are theoretically infinitesimally small. However, neither the PFD chip nor
the external charge pump/loop filter are perfect. Any leakage in the charge
pump and/or loop filter causes the PFD to continually output wider than
normal pulses in order to supply the additional charge current necessary to
make up for the current leakage. This results in a non-zero phase error at
the PFD inputs.

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.

In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

It's a common misconception to think of phase lock or even
phase control as trying to achieve a "zero degree" condition with
no phase offset. What is achieved in phase lock is a STABLE,
BUT OFFSET, phase relationship between signal and reference
frequencies at PFD inputs.

The easiest way to prove the condition is to scope an adjustable-
frequency PLL at the signal and reference PFD inputs and then
the '44-type PFD output into the loop filter. [measure the VCO
frequency separately if desired to prove the VCO, if desired] At
one locked frequency of the VCO the PFD output is a finite-width
pulse at the reference frequency. Change the divider setting for a
new VCO frequency and the PFD output has a different pulse
width. That can be confirmed by the DC control voltage...one value
at the first frequency setting, another value at the second frequency
setting. That DC control voltage is, in effect, an average value of
the pulse width out of the PFD.


I am struggling to understand the comment above that the AD9901 is not
suitable
for use in frequency synthesizers because of the large spurious sidebands
arising from its use. What causes the additional sidebands ?

As mentioned, the PFD output pulses approach zero width at lock, making it
easier to filter the pulses down to pure DC in the charge pump/loop filter.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

The XOR PD will output a 50% duty cycle pulse train at lock. This is much
more difficult to filter down to pure DC, resulting in modulation of the
VCO, and thus sidebands.

It is no different. Control voltage averaged out of an XOR phase
detector is still from essentially the same finite pulse width. [those
have worked for years without any comments about "spurs"]

The vast difference between an XOR PD and the '44-type PFD is
that the XOR PD is limited to a +/- 90 degree control and can't
tell the loop how to come off of a start-up condition which is way
off to one side of the VCO range or the other. The '44-type PFD
works over +/- 180 degree range and DOES indicate a way-off
VCO signal frequency condition. It will start up safely. In the
old PDs limited to 90 degree range, the general way of starting
up was with a very slow sawtooth generator algebraically adding
to the control voltage...once the lock range was achieved, more
circuitry shut off the sawtooth. [lots of extra parts]

In either type of phase detector, the amount of reference frequency
ripple out of the loop filter is dependent on the type of filter and the
speed of lock-in time on changing frequency of the VCO through
the divider setting. On can make the loop filter very slow and cut
the (awful, terrible) spurious sidebands down...and also waste
literal minutes waiting for the PLL to lock in.

Those (awful, terrible) spurs at increments of the reference
frequency are seldom worth worrying about in a PLL with good
shielding and decoupling around the control voltage parts of the
PLL. [the proof lies in tens of thousands of simple PLLs working
all around the globe without worries over "not working" because
their spurious outputs are "too high"]

Len Anderson
retired (from regular hours) electronic engineer person

Wrong on all counts Len!

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.
In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

In the digital PFD, there are essentially two outputs that drive the charge
storage circuit; "pump up" and "pump down". If there is a phase error, the
corresponding output produces pulses that are exactly proportional to the
time-error between the two PD inputs. If the time error corresponds to a
leading phase relationship between VCO and reference, then the "pump down"
output produces pulses equal in width to the lead time, discharging the
charge storage element. If there is a lagging relationship, then the "pump
up" output produces produces pulses equal in width to the lag time, charging
the charge storage element. If there is no error , then neither pump output
produces any pulses, and the charge storage element just 'holds' the last
charge it had on it. In a practical PFD implementation, it is impossible to
maintain the zero pulse-width point because the PFD is a digital feedback
circuit, and you would need parts with zero propagation delay to make such a
circuit. However, the width of the pulses in modern designs can get down
into the nanosecond range at lock. For this reason, the PFD can produce much
lower sideband content than the XOR, which outputs large pulses at lock. The
larger the output pulse, the more difficult the loop filter design.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

Wrong again! With large frequency errors, the PFD produces constant pumping.
If it didn't, it couldn't acquire with phase errors larger than 180deg.

You are also wrong in asserting that the lock-in range of the PFD is +/- 180
degrees. In fact, it is infinite (in theory). Yes, its linear output
compliance range is +/- 180 degrees, but it can acquire lock even when there
is an infinite frequency error. This is because once the PFD output exceeds
it's compliance range, it outputs a constant "pump up" or "pump down" pulse
train, which in turn causes the loop filter voltage to ramp up or down as
the case might be until the signal comes back into the compliance range and
lock is established. In practice the range is not infinite, only because you
can't build a VCO with infinite tuning range or a PFD with infinite clocking
speed.

The XOR's big advantage is that it is simple, and there is no discontinuity
around the phase lock point (as there is in the PFD), but it does not lock
up readily in the face of frequency errors. The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.

Joe
W3JDR



"Avery Fineman" wrote in message
...
In article , "W3JDR"

writes:

John,

Elsewhere in this thread there seems to have been some debate on the
operation
of the phase frequency detector. IMHO if the phase detector has a
tri-state
output then the loop over time must lock with no phase difference
between
the
reference and controlled signals, ie 0 degrees.

Theoretically, the edge controlled PFD locks the signal & reference with
0
degrees phase error. When the loop is locked, the output pulses from the
PFD
are theoretically infinitesimally small. However, neither the PFD chip
nor
the external charge pump/loop filter are perfect. Any leakage in the
charge
pump and/or loop filter causes the PFD to continually output wider than
normal pulses in order to supply the additional charge current necessary
to
make up for the current leakage. This results in a non-zero phase error
at
the PFD inputs.

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.

In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

It's a common misconception to think of phase lock or even
phase control as trying to achieve a "zero degree" condition with
no phase offset. What is achieved in phase lock is a STABLE,
BUT OFFSET, phase relationship between signal and reference
frequencies at PFD inputs.

The easiest way to prove the condition is to scope an adjustable-
frequency PLL at the signal and reference PFD inputs and then
the '44-type PFD output into the loop filter. [measure the VCO
frequency separately if desired to prove the VCO, if desired] At
one locked frequency of the VCO the PFD output is a finite-width
pulse at the reference frequency. Change the divider setting for a
new VCO frequency and the PFD output has a different pulse
width. That can be confirmed by the DC control voltage...one value
at the first frequency setting, another value at the second frequency
setting. That DC control voltage is, in effect, an average value of
the pulse width out of the PFD.


I am struggling to understand the comment above that the AD9901 is not
suitable
for use in frequency synthesizers because of the large spurious
sidebands
arising from its use. What causes the additional sidebands ?

As mentioned, the PFD output pulses approach zero width at lock, making
it
easier to filter the pulses down to pure DC in the charge pump/loop
filter.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

The XOR PD will output a 50% duty cycle pulse train at lock. This is much
more difficult to filter down to pure DC, resulting in modulation of the
VCO, and thus sidebands.

It is no different. Control voltage averaged out of an XOR phase
detector is still from essentially the same finite pulse width. [those
have worked for years without any comments about "spurs"]

The vast difference between an XOR PD and the '44-type PFD is
that the XOR PD is limited to a +/- 90 degree control and can't
tell the loop how to come off of a start-up condition which is way
off to one side of the VCO range or the other. The '44-type PFD
works over +/- 180 degree range and DOES indicate a way-off
VCO signal frequency condition. It will start up safely. In the
old PDs limited to 90 degree range, the general way of starting
up was with a very slow sawtooth generator algebraically adding
to the control voltage...once the lock range was achieved, more
circuitry shut off the sawtooth. [lots of extra parts]

In either type of phase detector, the amount of reference frequency
ripple out of the loop filter is dependent on the type of filter and
the
speed of lock-in time on changing frequency of the VCO through
the divider setting. On can make the loop filter very slow and cut
the (awful, terrible) spurious sidebands down...and also waste
literal minutes waiting for the PLL to lock in.

Those (awful, terrible) spurs at increments of the reference
frequency are seldom worth worrying about in a PLL with good
shielding and decoupling around the control voltage parts of the
PLL. [the proof lies in tens of thousands of simple PLLs working
all around the globe without worries over "not working" because
their spurious outputs are "too high"]

Len Anderson
retired (from regular hours) electronic engineer person

In article , "W3JDR"
writes:

Wrong on all counts Len!

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.
In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

In the digital PFD, there are essentially two outputs that drive the charge
storage circuit; "pump up" and "pump down". If there is a phase error, the
corresponding output produces pulses that are exactly proportional to the
time-error between the two PD inputs. If the time error corresponds to a
leading phase relationship between VCO and reference, then the "pump down"
output produces pulses equal in width to the lead time, discharging the
charge storage element. If there is a lagging relationship, then the "pump
up" output produces produces pulses equal in width to the lag time, charging
the charge storage element. If there is no error , then neither pump output
produces any pulses, and the charge storage element just 'holds' the last
charge it had on it.

Going to make it one of those long days? :-)

OK, so where is the VCO control voltage coming from and how does
it "know" how to reach the right voltage for the right frequency?

It doesn't...because the PFD output (MC4044 type) does not have
to. There will ALWAYS be a small error in any control loop...
otherwise a control loop couldn't function to do controlling (basic
control loop theory which so many seem to forget).

A "charge pump" is basically a voltage-to-current converter to
develop a basically-DC control voltage for the VCO of the PLL
after the loop filtering. One doesn't need to use the charge
pump in the MC4044 or the 11C44 chip. The digital output of
the PFD can go direct to the loop filter. Even with the charge
pump in-use, the whole thing (pump and loop filter or integrator/
filter) simply integrates a time variation (width of repetitious
pulses out of PFD) into a stable DC value.

In a practical PFD implementation, it is impossible to
maintain the zero pulse-width point because the PFD is a digital feedback
circuit, and you would need parts with zero propagation delay to make such a
circuit.

Absolutely not. There must be SOME gate delay. If there were
zero, then every single D or J-K flip-flop would not work! Since
they do work, there is always SOME internal gate delay.

That internal IC capacitance causing the delay is the cause for all
that heat-dissipation effort on hundred-thousand-plus transistor
junction ICs used in single-chip microcomputers. In a 9- or 10-gate
IC there isn't a lot of heat rise...but the parasitic gate structure
capacitance is always there and all gates have finitie propagation
delays.

Some number of years ago I went into the old databooks (so far
back they were free for anyone and still had the equivalent circuits
in them...like thirty plus years ago) and started doing timing
diagrams to see EXACTLY how they worked. Most interesting bit
of "reverse engineering" and also quite interesting.

The '44-type PFD digital part is essentially a very complex D FF
like structure and it triggers only one direction of transition edges
(like the Ds and J-Ks). The '44 is more complex in trying to see
how it works due to the various conditions of relative input phases.
If there are more than two signal edges for every reference edge,
the outputs hold at one state indicating a "way-off" towards the
high frequency range end of the signal. If there are more than
two reference edges for every signal edge, the outputs flip to the
other state...the "way-off" signal frequency is too low.

However, when there is one input edge for each other input edge,
the outputs produce a variable-width pulse, repetition rate equal
to the reference frequency, which corresponds to the relative
phase of the two inputs. The outputs are always "flipping" when
the inputs are at the same frequency even though the inputs
need NOT be in exact phase positioning. Not a problem. That
variable width turns out to be extremely good for control since a
simple integrator can convert the variable time into a variable
voltage whose DC value is proportional to the relative inputs
phase displacement.

An op-amp integrator circuit functions as a sort of time-to-current-
to-output-voltage converter (technically, the input R is creating a
pseudo-constant-current source for the mid-point of R and C of
the integrator op-amp input). That can also be used as a "Type 1"
loop filter. With some modifications of a basic integrator, it
can become any of the other types. Or, one can, with a sensitive
control voltage characteristic of the VCO, use a passive loop
filter with the filter input directly on the PFD output (choose either
one to go with polarity of the VCO control needed). For that
alternate condition, the PFD Vcc *MUST* be stable and decoupled
less it mess around with more badness in the control voltage.
The "charge pump" circuit of the MC4044/11C44 is really optional
to use. It isn't absolutely necessary although it can cut down on
the number of parts used.

Based on hands-on observation of several of these PLLs, especially
those of PFDs made from individual logic gates, the PFD outputs
ARE pulses at the reference frequency repetition rate. Their width
is proportional to the integrated-averaged DC control voltage of the
VCO when in lock.

If what you say is true, then there would be ZERO control voltage
out of any of the mentioned interface circuits. Obviously, there
must be some finite amount of control voltage for the VCO to
adjust to a particular PLL frequency increment. That control
voltage is the integrated-averaged DC out of the loop filter, not
some mythical "charged whatsis" from that charge pump.

In looking at the relative phases of the signal and reference AC
inputs, the loop is LOCKED even though the phases are
offset. The phases remain "in step" and unchanging on the
'scope but they are offset in phase from one another. [that's
normal with this kind of PFD and PLL] I've been looking at
these things for about three decades and see the same things.
With the MC145151 combo PLL chip I'm playing with now, the
PFD gates aren't fully available for peeking, but it locks in as
advertised as I said above.

However, the width of the pulses in modern designs can get down
into the nanosecond range at lock.

Nobody, not even the PLL really cares. How much voltage are
you going to generate on the VCO control line from nanosecond
pulse widths at a 1 KHz reference input repetition rate? Very
little.

For this reason, the PFD can produce much
lower sideband content than the XOR, which outputs large pulses at lock. The
larger the output pulse, the more difficult the loop filter design.

The only thing "difficult" about a PLL is others paying attention to
the REQUIRED values of control voltage gain and the reference
frequency AND the simple math needed to calculate those values.
"Difficult" is when the control voltage isn't linear over frequency
(which upsets the heck out of the control gain at one end of the
VCO range). "Difficult" is not paying attention to the subcircuit
isolation and shielding and decoupling that produces the control
voltage where it is ripe for picking up garbage that results in all
kinds of badness in VCO stability.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

Wrong again! With large frequency errors, the PFD produces constant pumping.
If it didn't, it couldn't acquire with phase errors larger than 180deg.

No. If you examine the states of all gates in a '44 PFD with
corresponding input waveform states, you will see that the
"way-off" (phase errors larger than 180 degrees) conditions of
the PFD outputs REMAIN in their fully-on or fully-off states.
That's the gem of this gate arrangement and the key to coming
into lock on power-up.

One reason I submitted my article to Jim Fisk at Ham Radio
magazine (it was not in the original sequence at the start of that
series) was as a result of trying to explain the gate-states of the
'44 PFD to another. The waveform timing diagrams in that
September 1982 article accurately show the state changes
(without the precise amount of internal gate delay, not really
needed in explanation). Just to make certain, I'd duplicated the
gate logic in an Apple ][ program to make sure...and to see the
variations in original conditions that might cause a bad start-up.
I didn't use the conventional bubble-and-arrow state change
diagrams since so few contemporaries could "read" them and
I didn't much care for that kind of presentation either. Waveforms
were an old familiar thing and I stuck with that.

You are also wrong in asserting that the lock-in range of the PFD is +/- 180
degrees. In fact, it is infinite (in theory).

"Infinite" only in the grossest sense of being - in effect - locked
up on either of the "way-off" conditions. From what I gather, it
was designed to do that very thing. An excellent thing to insure
start-up.

However, integrated-averaged to DC, the outputs of the PFD make
an excellent phase meter with a DC that can be converted to
binary in an A-to-D. The Rocketdyne Deformable Mirror project
used that characteristic to measure the heterodyned optical
signals from the optics at 1 MHz PFD input. It worked just fine
out to about +/- 179 degrees or so when calibrated for the whole
optical-electronic loop. [optics could approach 180 but never
quite get exactly there...but then that's difficult with electronics
also, needing time-interval averaging counters and such which
we DID use...but the optics folks wanted to tweak their stable
table optics more than tweaking instrument dials...:-)]

Yes, its linear output
compliance range is +/- 180 degrees, but it can acquire lock even when there
is an infinite frequency error. This is because once the PFD output exceeds
it's compliance range, it outputs a constant "pump up" or "pump down" pulse
train, which in turn causes the loop filter voltage to ramp up or down as
the case might be until the signal comes back into the compliance range and
lock is established.

No. At beyond-control-range input frequencies, the PFD outputs
go to their stable, unchanging "way-off" states and stay there
until both inputs are the same frequency. Ain't no "pump" pulses
whatsoever at those "way-off" conditions.

The XOR's big advantage is that it is simple, and there is no discontinuity
around the phase lock point (as there is in the PFD), but it does not lock
up readily in the face of frequency errors. The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.

In practice, since the last days of WW2, phase-frequency control
loops have used lots of extra circuitry to cure that start-up. Philco
did that with some S-band microwave radio relay gear used by the
USAF in 1955. Army used L-band crystal-controlled microwave
radio relay terminals by GE, had no problems. USAF had Philco
tech reps there seemingly all the time since their frequency control
tended to pop off lock and go sweeping frequency a lot from their
extra sawtooth circuitry. [PLL was first disclosed in 1932 by
"H. de Bellecize, working in France" according to my giant
1980 50th anniversary special edition of Electronics magazine]

There have been a few PFD circuits devised before the '44 type
but I'd say the '44 went all the way to excellence with elegance
in its simplicity. There have been at least one close to the '44
but arranged differently and with more internal parts...but that one
works about the same as the '44.

When you get the chance, grab a 'scope and look into the
waveforms of a PFD as well as the control voltage. You will
find out I'm right. No "theory" on that, just working PLL
hardware. I've seen and observed that, used the basic
knowledge to build my own PLLs (including a couple just for
me) and am confident in the explanation I gave. They WORK
by all the nice instruments from Hewlett and Packard (rest
their souls).

Len Anderson
retired (from regular hours) electronic engineer person

"Avery Fineman" wrote in message
...

In article , "W3JDR"

writes:

To Len:
Not quite it. In order to derive a control voltage for the
controlled
oscillator, the PFD output MUST BE A FINITE WIDTH....

...BUT THERE IS ALWAYS A PHASE OFFSET.



Len,

This is actually _not_ the case as Joe (W3JDR), says.



Summary: The charge pump drives CURRENT into the main loop filter
capacitor forming another pole (at the origin, if I recall my control theory
correctly) or _integrator_.



Detail = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
= = = = =

The charge pump is set up as follows. The PFD has two outputs, an UP
and DOWN. The UP output produces an output which is "active" or high (lets
make everything positive-true logic for this discussion) for a time period
which is the time from the edge of the reference to the edge of the VCO. So
that when the VCO drifts down, its edge is later and we get pulses. In
other words, we get pulses out equal to the time difference of the edges.
The DOWN is the converse.



Each output drives one half of the charge pump and as long as that
output is in its "active" state, the charge pump is providing _current_ into
the main loop filter capacitor. (lets assume that UP "pulses" means the VCO
it too low and VCO freq is proportinal to control voltage) When you get off
freq. the respective PFD output hits the rail and is in a _constant_ UP
state. Therefore, that half of the charge pump drives current into the
capacitor causing it to charge up at a rate equal to I/C. This is a simple
re-write of the capacitor formula I = C * dv/dt. This effect is another
integrator in the loop which gets you to zero phase error. As long as there
is a phase error, there will be a _CHANGE_ in control (or steering) line
voltage until you get to zero phase error and a stable control line.



If I again recall my control theory, this makes it a type 2 loop.



This does TWO things.

1) It drives the PFD pulses to zero making them as small as the logic
will allow thus

leaving the least amount of reference frequency energy to be removed
and

2) The integrator attenuates the higher freq harmonics of the reference
pulses that remain.

To be honest at this point, the loop filter will be a lag filter
which has

a finite high freq atten, but some loss none the less. Other
filtering is usually

required to further reduce the reference spurs. In communications
PLLs the fight

is between the filtering required to get the reference spurs down to
the desired

level and the classical lock time determining "loop filter". This
is because the phase of the reference spur

low pass filter starts to eat into the loop's phase margin and cause
more

ringing (poorer damping factor) as you require more reference
attenuation.

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
= =

.......


OK, so where is the VCO control voltage coming from and how does
it "know" how to reach the right voltage for the right frequency?



From the loop filter capacitor which stays charged when the PFD shuts up
at zero phase error.

....
...There will ALWAYS be a small error in any control loop...
otherwise a control loop couldn't function to do controlling (basic
control loop theory which so many seem to forget).



You are thinking of a type one loop and that's ok... Add the integrator
and (by theory & practice) you get zero phase error. I majored in control
theory & designed 2-way mobile PLL synthesizers. I also believe I designed
and built the first amateur, PLL synthesized 2M handheld (Motorola HT220) in
1973.



A "charge pump" is basically a voltage-to-current converter to...



Actually, Len, the charge pumps I designed were a phase-to-*current*
converter. (Actually an edge-time-difference - to - current converter.
That is, when combined with the PFD. By itself, it was a pulse to current
pulse converter. It was a current source which was turned on during the
pulse. (two--one for UP & one for DOWN). Perhaps it should be called a
"gated current source". During the UP or DOWN pulse, the respective current
source is turned on at its full current.




... zero propagation delay to make such a...



If I recall the Fairchild improved 4044 used MATCHED delays in the two
paths to minimize the dead zone as well as the opposite effect, overlap.



...The '44 is more complex...
If there are more than two signal edges for every reference edge,
the outputs hold at one state indicating a "way-off" ...



Yea, off frequency. So you DO know how it works by this statement. The
phrase "hold at one state" _IS_ the key here in the charge-pump circuit. It
will "hold the charge pump transistor on", continue to supply current
(charge at a constant rate) to the cap causing the voltage to keep rising
and the frequency to keep changing. When the phase error is zero, then the
control line stops changing and the VCO is on freq.




An op-amp integrator circuit functions as a sort of time-to-current-
to-output-voltage converter ...



Ahhh! The "charge pump" does the same thing as a regular
integrator…increasing the loop type.





Based on hands-on observation … the PFD outputs
ARE pulses at the reference frequency… Their width
is proportional to the integrated-averaged DC control voltage of the
VCO when in lock.



You may have lost me here, Len. I think, in the type 1 loop you
describe, the control voltage is the average-of-the-pulses (the phase
error). I think you mean the "average of", not "integrated average of".



With the type 1 loop the VCO control line voltage would be the average of
the phase error. So you would indeed require an error, but that's why we
add the integration function in some loops.

Please note that by virtue of the VCO (having a voltage-to-frequency
transfer characteristic) and the Phase detector (having a phase to voltage
characteristic), there is already one built-in integration in the loop.
This is because phase is the integral of frequency...or is it the other way
'round. (i always have to stop and draw a figure to state this freq/phase
integral relationship...les-see...– a step freq change integrates to a
ramp--phase is the integral of freq, yea, that's it )




As I said earlier, I have watched the loop bounce around the dead zone -
bumping up against the ends of the (zero phase) dead zone and producing mini
correction charges to correct the frequency. I would often force some small
current (sometimes with a reverse biased germanium diode) to stop the rumble
by forcing a small phase error.



Each integration in the loop gets you another level of "in lock"
accuracy. (i forget the official term), but…

First is a frequency locked loop where, as you say here, there must be a
small Frequency error to obtain the VCO voltage. Such as using a VCO with a
discriminator instead of a PD. (frequency type 0)

Second is frequency lock loop with fixed phase error. (frequency type 1 –
phase type 0)

Third is the one with zero phase error. (frequency type 2)...etc



Each increase in type (or addition of a loop integrator) gets to a true
_zero error_ for a higher order of input change. Starting with (although
trivial a frequency locked loop with finite frequency error), freq, then
phase, then ramping phase, then second order phase change (squared) ...but i
digress...




...the "way-off" (phase errors larger than 180 degrees) conditions of
the PFD outputs REMAIN in their fully-on ...



This is what Len meant, I believe, by "constant pumping". Not your
usual, water-well pump metaphor, Len.





You get near the subject of "Capture Range" and "Lock Range" next. The
XOR type PD has a lock range , or "pull-in Range" determined, in part, by
the loop filter. More correctly by the loop bandwidth. If some of the XOR
output square wave can't get through the loop filter (by being a low enough
frequency) and drive the VCO toward the desired frequency, then it can't
lock from far off freq. So it has a finite capture or pull-in frequency
range. The PFD has an infinite pull-in (within the rails) per the above
operation.





...However, integrated-averaged to DC, the outputs of the PFD make
an excellent phase meter …



(again I dislike the term "integrated average" here, but think "average"
is what is intended) Very true (Without the charge pump). Just averaging
the pulse width (phase difference). It is a phase-to-voltage converter.
Then voltage makes the VCO get to freq.


...Ain't no "pump" pulses whatsoever at those "way-off" conditions.



Very true if you mean "pulses" with an off-time in between. Just a
steady always on "pump" current at full current. This translates to
"maximum ramp speed" of the VCO control line.


Joe

The XOR's big advantage is that it is simple, and there is no
discontinuity
around the phase lock point (as there is in the PFD), but it does not
lock
up readily in the face of frequency errors.



You should say; "in the face of _large_ frequency errors".... the
"Capture Range" problem I mentioned above.



Joe:

The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.



Yep. Sorta' the ideal. Almost zero reference pulse energy and pull-in
range limited by the PFD rails and VCO range only.


When you get the chance, grab a 'scope and look into the
waveforms of a PFD as well as the control voltage. You will
find out I'm right. No "theory" on that, just working PLL
hardware.



As long as you have no charge pump or integrator, you are 100% correct.
Len. All the Motorola Pulsar car phones used the same charge pump for 0
phase error. This is still used now, but fractional N methods allow small
steps in freq (~5 kc) with high reference frequencies (~2 Mc) at the expense
of more logic.



If I confused who said what, I apologize.
--
Steve N, K,9;d, c. i My email has no u's.

"Avery Fineman" wrote in message
...

In article , "W3JDR"

writes:

To Len:
Not quite it. In order to derive a control voltage for the
controlled
oscillator, the PFD output MUST BE A FINITE WIDTH....

...BUT THERE IS ALWAYS A PHASE OFFSET.



Len,

This is actually _not_ the case as Joe (W3JDR), says.



Summary: The charge pump drives CURRENT into the main loop filter
capacitor forming another pole (at the origin, if I recall my control theory
correctly) or _integrator_.



Detail = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
= = = = =

The charge pump is set up as follows. The PFD has two outputs, an UP
and DOWN. The UP output produces an output which is "active" or high (lets
make everything positive-true logic for this discussion) for a time period
which is the time from the edge of the reference to the edge of the VCO. So
that when the VCO drifts down, its edge is later and we get pulses. In
other words, we get pulses out equal to the time difference of the edges.
The DOWN is the converse.



Each output drives one half of the charge pump and as long as that
output is in its "active" state, the charge pump is providing _current_ into
the main loop filter capacitor. (lets assume that UP "pulses" means the VCO
it too low and VCO freq is proportinal to control voltage) When you get off
freq. the respective PFD output hits the rail and is in a _constant_ UP
state. Therefore, that half of the charge pump drives current into the
capacitor causing it to charge up at a rate equal to I/C. This is a simple
re-write of the capacitor formula I = C * dv/dt. This effect is another
integrator in the loop which gets you to zero phase error. As long as there
is a phase error, there will be a _CHANGE_ in control (or steering) line
voltage until you get to zero phase error and a stable control line.



If I again recall my control theory, this makes it a type 2 loop.



This does TWO things.

1) It drives the PFD pulses to zero making them as small as the logic
will allow thus

leaving the least amount of reference frequency energy to be removed
and

2) The integrator attenuates the higher freq harmonics of the reference
pulses that remain.

To be honest at this point, the loop filter will be a lag filter
which has

a finite high freq atten, but some loss none the less. Other
filtering is usually

required to further reduce the reference spurs. In communications
PLLs the fight

is between the filtering required to get the reference spurs down to
the desired

level and the classical lock time determining "loop filter". This
is because the phase of the reference spur

low pass filter starts to eat into the loop's phase margin and cause
more

ringing (poorer damping factor) as you require more reference
attenuation.

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
= =

.......


OK, so where is the VCO control voltage coming from and how does
it "know" how to reach the right voltage for the right frequency?



From the loop filter capacitor which stays charged when the PFD shuts up
at zero phase error.

....
...There will ALWAYS be a small error in any control loop...
otherwise a control loop couldn't function to do controlling (basic
control loop theory which so many seem to forget).



You are thinking of a type one loop and that's ok... Add the integrator
and (by theory & practice) you get zero phase error. I majored in control
theory & designed 2-way mobile PLL synthesizers. I also believe I designed
and built the first amateur, PLL synthesized 2M handheld (Motorola HT220) in
1973.



A "charge pump" is basically a voltage-to-current converter to...



Actually, Len, the charge pumps I designed were a phase-to-*current*
converter. (Actually an edge-time-difference - to - current converter.
That is, when combined with the PFD. By itself, it was a pulse to current
pulse converter. It was a current source which was turned on during the
pulse. (two--one for UP & one for DOWN). Perhaps it should be called a
"gated current source". During the UP or DOWN pulse, the respective current
source is turned on at its full current.




... zero propagation delay to make such a...



If I recall the Fairchild improved 4044 used MATCHED delays in the two
paths to minimize the dead zone as well as the opposite effect, overlap.



...The '44 is more complex...
If there are more than two signal edges for every reference edge,
the outputs hold at one state indicating a "way-off" ...



Yea, off frequency. So you DO know how it works by this statement. The
phrase "hold at one state" _IS_ the key here in the charge-pump circuit. It
will "hold the charge pump transistor on", continue to supply current
(charge at a constant rate) to the cap causing the voltage to keep rising
and the frequency to keep changing. When the phase error is zero, then the
control line stops changing and the VCO is on freq.




An op-amp integrator circuit functions as a sort of time-to-current-
to-output-voltage converter ...



Ahhh! The "charge pump" does the same thing as a regular
integrator…increasing the loop type.





Based on hands-on observation … the PFD outputs
ARE pulses at the reference frequency… Their width
is proportional to the integrated-averaged DC control voltage of the
VCO when in lock.



You may have lost me here, Len. I think, in the type 1 loop you
describe, the control voltage is the average-of-the-pulses (the phase
error). I think you mean the "average of", not "integrated average of".



With the type 1 loop the VCO control line voltage would be the average of
the phase error. So you would indeed require an error, but that's why we
add the integration function in some loops.

Please note that by virtue of the VCO (having a voltage-to-frequency
transfer characteristic) and the Phase detector (having a phase to voltage
characteristic), there is already one built-in integration in the loop.
This is because phase is the integral of frequency...or is it the other way
'round. (i always have to stop and draw a figure to state this freq/phase
integral relationship...les-see...– a step freq change integrates to a
ramp--phase is the integral of freq, yea, that's it )




As I said earlier, I have watched the loop bounce around the dead zone -
bumping up against the ends of the (zero phase) dead zone and producing mini
correction charges to correct the frequency. I would often force some small
current (sometimes with a reverse biased germanium diode) to stop the rumble
by forcing a small phase error.



Each integration in the loop gets you another level of "in lock"
accuracy. (i forget the official term), but…

First is a frequency locked loop where, as you say here, there must be a
small Frequency error to obtain the VCO voltage. Such as using a VCO with a
discriminator instead of a PD. (frequency type 0)

Second is frequency lock loop with fixed phase error. (frequency type 1 –
phase type 0)

Third is the one with zero phase error. (frequency type 2)...etc



Each increase in type (or addition of a loop integrator) gets to a true
_zero error_ for a higher order of input change. Starting with (although
trivial a frequency locked loop with finite frequency error), freq, then
phase, then ramping phase, then second order phase change (squared) ...but i
digress...




...the "way-off" (phase errors larger than 180 degrees) conditions of
the PFD outputs REMAIN in their fully-on ...



This is what Len meant, I believe, by "constant pumping". Not your
usual, water-well pump metaphor, Len.





You get near the subject of "Capture Range" and "Lock Range" next. The
XOR type PD has a lock range , or "pull-in Range" determined, in part, by
the loop filter. More correctly by the loop bandwidth. If some of the XOR
output square wave can't get through the loop filter (by being a low enough
frequency) and drive the VCO toward the desired frequency, then it can't
lock from far off freq. So it has a finite capture or pull-in frequency
range. The PFD has an infinite pull-in (within the rails) per the above
operation.





...However, integrated-averaged to DC, the outputs of the PFD make
an excellent phase meter …



(again I dislike the term "integrated average" here, but think "average"
is what is intended) Very true (Without the charge pump). Just averaging
the pulse width (phase difference). It is a phase-to-voltage converter.
Then voltage makes the VCO get to freq.


...Ain't no "pump" pulses whatsoever at those "way-off" conditions.



Very true if you mean "pulses" with an off-time in between. Just a
steady always on "pump" current at full current. This translates to
"maximum ramp speed" of the VCO control line.


Joe

The XOR's big advantage is that it is simple, and there is no
discontinuity
around the phase lock point (as there is in the PFD), but it does not
lock
up readily in the face of frequency errors.



You should say; "in the face of _large_ frequency errors".... the
"Capture Range" problem I mentioned above.



Joe:

The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.



Yep. Sorta' the ideal. Almost zero reference pulse energy and pull-in
range limited by the PFD rails and VCO range only.


When you get the chance, grab a 'scope and look into the
waveforms of a PFD as well as the control voltage. You will
find out I'm right. No "theory" on that, just working PLL
hardware.



As long as you have no charge pump or integrator, you are 100% correct.
Len. All the Motorola Pulsar car phones used the same charge pump for 0
phase error. This is still used now, but fractional N methods allow small
steps in freq (~5 kc) with high reference frequencies (~2 Mc) at the expense
of more logic.



If I confused who said what, I apologize.
--
Steve N, K,9;d, c. i My email has no u's.

In article , "W3JDR"
writes:

Wrong on all counts Len!

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.
In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

In the digital PFD, there are essentially two outputs that drive the charge
storage circuit; "pump up" and "pump down". If there is a phase error, the
corresponding output produces pulses that are exactly proportional to the
time-error between the two PD inputs. If the time error corresponds to a
leading phase relationship between VCO and reference, then the "pump down"
output produces pulses equal in width to the lead time, discharging the
charge storage element. If there is a lagging relationship, then the "pump
up" output produces produces pulses equal in width to the lag time, charging
the charge storage element. If there is no error , then neither pump output
produces any pulses, and the charge storage element just 'holds' the last
charge it had on it.

Going to make it one of those long days? :-)

OK, so where is the VCO control voltage coming from and how does
it "know" how to reach the right voltage for the right frequency?

It doesn't...because the PFD output (MC4044 type) does not have
to. There will ALWAYS be a small error in any control loop...
otherwise a control loop couldn't function to do controlling (basic
control loop theory which so many seem to forget).

A "charge pump" is basically a voltage-to-current converter to
develop a basically-DC control voltage for the VCO of the PLL
after the loop filtering. One doesn't need to use the charge
pump in the MC4044 or the 11C44 chip. The digital output of
the PFD can go direct to the loop filter. Even with the charge
pump in-use, the whole thing (pump and loop filter or integrator/
filter) simply integrates a time variation (width of repetitious
pulses out of PFD) into a stable DC value.

In a practical PFD implementation, it is impossible to
maintain the zero pulse-width point because the PFD is a digital feedback
circuit, and you would need parts with zero propagation delay to make such a
circuit.

Absolutely not. There must be SOME gate delay. If there were
zero, then every single D or J-K flip-flop would not work! Since
they do work, there is always SOME internal gate delay.

That internal IC capacitance causing the delay is the cause for all
that heat-dissipation effort on hundred-thousand-plus transistor
junction ICs used in single-chip microcomputers. In a 9- or 10-gate
IC there isn't a lot of heat rise...but the parasitic gate structure
capacitance is always there and all gates have finitie propagation
delays.

Some number of years ago I went into the old databooks (so far
back they were free for anyone and still had the equivalent circuits
in them...like thirty plus years ago) and started doing timing
diagrams to see EXACTLY how they worked. Most interesting bit
of "reverse engineering" and also quite interesting.

The '44-type PFD digital part is essentially a very complex D FF
like structure and it triggers only one direction of transition edges
(like the Ds and J-Ks). The '44 is more complex in trying to see
how it works due to the various conditions of relative input phases.
If there are more than two signal edges for every reference edge,
the outputs hold at one state indicating a "way-off" towards the
high frequency range end of the signal. If there are more than
two reference edges for every signal edge, the outputs flip to the
other state...the "way-off" signal frequency is too low.

However, when there is one input edge for each other input edge,
the outputs produce a variable-width pulse, repetition rate equal
to the reference frequency, which corresponds to the relative
phase of the two inputs. The outputs are always "flipping" when
the inputs are at the same frequency even though the inputs
need NOT be in exact phase positioning. Not a problem. That
variable width turns out to be extremely good for control since a
simple integrator can convert the variable time into a variable
voltage whose DC value is proportional to the relative inputs
phase displacement.

An op-amp integrator circuit functions as a sort of time-to-current-
to-output-voltage converter (technically, the input R is creating a
pseudo-constant-current source for the mid-point of R and C of
the integrator op-amp input). That can also be used as a "Type 1"
loop filter. With some modifications of a basic integrator, it
can become any of the other types. Or, one can, with a sensitive
control voltage characteristic of the VCO, use a passive loop
filter with the filter input directly on the PFD output (choose either
one to go with polarity of the VCO control needed). For that
alternate condition, the PFD Vcc *MUST* be stable and decoupled
less it mess around with more badness in the control voltage.
The "charge pump" circuit of the MC4044/11C44 is really optional
to use. It isn't absolutely necessary although it can cut down on
the number of parts used.

Based on hands-on observation of several of these PLLs, especially
those of PFDs made from individual logic gates, the PFD outputs
ARE pulses at the reference frequency repetition rate. Their width
is proportional to the integrated-averaged DC control voltage of the
VCO when in lock.

If what you say is true, then there would be ZERO control voltage
out of any of the mentioned interface circuits. Obviously, there
must be some finite amount of control voltage for the VCO to
adjust to a particular PLL frequency increment. That control
voltage is the integrated-averaged DC out of the loop filter, not
some mythical "charged whatsis" from that charge pump.

In looking at the relative phases of the signal and reference AC
inputs, the loop is LOCKED even though the phases are
offset. The phases remain "in step" and unchanging on the
'scope but they are offset in phase from one another. [that's
normal with this kind of PFD and PLL] I've been looking at
these things for about three decades and see the same things.
With the MC145151 combo PLL chip I'm playing with now, the
PFD gates aren't fully available for peeking, but it locks in as
advertised as I said above.

However, the width of the pulses in modern designs can get down
into the nanosecond range at lock.

Nobody, not even the PLL really cares. How much voltage are
you going to generate on the VCO control line from nanosecond
pulse widths at a 1 KHz reference input repetition rate? Very
little.

For this reason, the PFD can produce much
lower sideband content than the XOR, which outputs large pulses at lock. The
larger the output pulse, the more difficult the loop filter design.

The only thing "difficult" about a PLL is others paying attention to
the REQUIRED values of control voltage gain and the reference
frequency AND the simple math needed to calculate those values.
"Difficult" is when the control voltage isn't linear over frequency
(which upsets the heck out of the control gain at one end of the
VCO range). "Difficult" is not paying attention to the subcircuit
isolation and shielding and decoupling that produces the control
voltage where it is ripe for picking up garbage that results in all
kinds of badness in VCO stability.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

Wrong again! With large frequency errors, the PFD produces constant pumping.
If it didn't, it couldn't acquire with phase errors larger than 180deg.

No. If you examine the states of all gates in a '44 PFD with
corresponding input waveform states, you will see that the
"way-off" (phase errors larger than 180 degrees) conditions of
the PFD outputs REMAIN in their fully-on or fully-off states.
That's the gem of this gate arrangement and the key to coming
into lock on power-up.

One reason I submitted my article to Jim Fisk at Ham Radio
magazine (it was not in the original sequence at the start of that
series) was as a result of trying to explain the gate-states of the
'44 PFD to another. The waveform timing diagrams in that
September 1982 article accurately show the state changes
(without the precise amount of internal gate delay, not really
needed in explanation). Just to make certain, I'd duplicated the
gate logic in an Apple ][ program to make sure...and to see the
variations in original conditions that might cause a bad start-up.
I didn't use the conventional bubble-and-arrow state change
diagrams since so few contemporaries could "read" them and
I didn't much care for that kind of presentation either. Waveforms
were an old familiar thing and I stuck with that.

You are also wrong in asserting that the lock-in range of the PFD is +/- 180
degrees. In fact, it is infinite (in theory).

"Infinite" only in the grossest sense of being - in effect - locked
up on either of the "way-off" conditions. From what I gather, it
was designed to do that very thing. An excellent thing to insure
start-up.

However, integrated-averaged to DC, the outputs of the PFD make
an excellent phase meter with a DC that can be converted to
binary in an A-to-D. The Rocketdyne Deformable Mirror project
used that characteristic to measure the heterodyned optical
signals from the optics at 1 MHz PFD input. It worked just fine
out to about +/- 179 degrees or so when calibrated for the whole
optical-electronic loop. [optics could approach 180 but never
quite get exactly there...but then that's difficult with electronics
also, needing time-interval averaging counters and such which
we DID use...but the optics folks wanted to tweak their stable
table optics more than tweaking instrument dials...:-)]

Yes, its linear output
compliance range is +/- 180 degrees, but it can acquire lock even when there
is an infinite frequency error. This is because once the PFD output exceeds
it's compliance range, it outputs a constant "pump up" or "pump down" pulse
train, which in turn causes the loop filter voltage to ramp up or down as
the case might be until the signal comes back into the compliance range and
lock is established.

No. At beyond-control-range input frequencies, the PFD outputs
go to their stable, unchanging "way-off" states and stay there
until both inputs are the same frequency. Ain't no "pump" pulses
whatsoever at those "way-off" conditions.

The XOR's big advantage is that it is simple, and there is no discontinuity
around the phase lock point (as there is in the PFD), but it does not lock
up readily in the face of frequency errors. The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.

In practice, since the last days of WW2, phase-frequency control
loops have used lots of extra circuitry to cure that start-up. Philco
did that with some S-band microwave radio relay gear used by the
USAF in 1955. Army used L-band crystal-controlled microwave
radio relay terminals by GE, had no problems. USAF had Philco
tech reps there seemingly all the time since their frequency control
tended to pop off lock and go sweeping frequency a lot from their
extra sawtooth circuitry. [PLL was first disclosed in 1932 by
"H. de Bellecize, working in France" according to my giant
1980 50th anniversary special edition of Electronics magazine]

There have been a few PFD circuits devised before the '44 type
but I'd say the '44 went all the way to excellence with elegance
in its simplicity. There have been at least one close to the '44
but arranged differently and with more internal parts...but that one
works about the same as the '44.

When you get the chance, grab a 'scope and look into the
waveforms of a PFD as well as the control voltage. You will
find out I'm right. No "theory" on that, just working PLL
hardware. I've seen and observed that, used the basic
knowledge to build my own PLLs (including a couple just for
me) and am confident in the explanation I gave. They WORK
by all the nice instruments from Hewlett and Packard (rest
their souls).

Len Anderson
retired (from regular hours) electronic engineer person

Wrong on all counts Len!

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.
In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

In the digital PFD, there are essentially two outputs that drive the charge
storage circuit; "pump up" and "pump down". If there is a phase error, the
corresponding output produces pulses that are exactly proportional to the
time-error between the two PD inputs. If the time error corresponds to a
leading phase relationship between VCO and reference, then the "pump down"
output produces pulses equal in width to the lead time, discharging the
charge storage element. If there is a lagging relationship, then the "pump
up" output produces produces pulses equal in width to the lag time, charging
the charge storage element. If there is no error , then neither pump output
produces any pulses, and the charge storage element just 'holds' the last
charge it had on it. In a practical PFD implementation, it is impossible to
maintain the zero pulse-width point because the PFD is a digital feedback
circuit, and you would need parts with zero propagation delay to make such a
circuit. However, the width of the pulses in modern designs can get down
into the nanosecond range at lock. For this reason, the PFD can produce much
lower sideband content than the XOR, which outputs large pulses at lock. The
larger the output pulse, the more difficult the loop filter design.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

Wrong again! With large frequency errors, the PFD produces constant pumping.
If it didn't, it couldn't acquire with phase errors larger than 180deg.

You are also wrong in asserting that the lock-in range of the PFD is +/- 180
degrees. In fact, it is infinite (in theory). Yes, its linear output
compliance range is +/- 180 degrees, but it can acquire lock even when there
is an infinite frequency error. This is because once the PFD output exceeds
it's compliance range, it outputs a constant "pump up" or "pump down" pulse
train, which in turn causes the loop filter voltage to ramp up or down as
the case might be until the signal comes back into the compliance range and
lock is established. In practice the range is not infinite, only because you
can't build a VCO with infinite tuning range or a PFD with infinite clocking
speed.

The XOR's big advantage is that it is simple, and there is no discontinuity
around the phase lock point (as there is in the PFD), but it does not lock
up readily in the face of frequency errors. The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.

Joe
W3JDR



"Avery Fineman" wrote in message
...
In article , "W3JDR"

writes:

John,

Elsewhere in this thread there seems to have been some debate on the
operation
of the phase frequency detector. IMHO if the phase detector has a
tri-state
output then the loop over time must lock with no phase difference
between
the
reference and controlled signals, ie 0 degrees.

Theoretically, the edge controlled PFD locks the signal & reference with
0
degrees phase error. When the loop is locked, the output pulses from the
PFD
are theoretically infinitesimally small. However, neither the PFD chip
nor
the external charge pump/loop filter are perfect. Any leakage in the
charge
pump and/or loop filter causes the PFD to continually output wider than
normal pulses in order to supply the additional charge current necessary
to
make up for the current leakage. This results in a non-zero phase error
at
the PFD inputs.

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.

In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

It's a common misconception to think of phase lock or even
phase control as trying to achieve a "zero degree" condition with
no phase offset. What is achieved in phase lock is a STABLE,
BUT OFFSET, phase relationship between signal and reference
frequencies at PFD inputs.

The easiest way to prove the condition is to scope an adjustable-
frequency PLL at the signal and reference PFD inputs and then
the '44-type PFD output into the loop filter. [measure the VCO
frequency separately if desired to prove the VCO, if desired] At
one locked frequency of the VCO the PFD output is a finite-width
pulse at the reference frequency. Change the divider setting for a
new VCO frequency and the PFD output has a different pulse
width. That can be confirmed by the DC control voltage...one value
at the first frequency setting, another value at the second frequency
setting. That DC control voltage is, in effect, an average value of
the pulse width out of the PFD.


I am struggling to understand the comment above that the AD9901 is not
suitable
for use in frequency synthesizers because of the large spurious
sidebands
arising from its use. What causes the additional sidebands ?

As mentioned, the PFD output pulses approach zero width at lock, making
it
easier to filter the pulses down to pure DC in the charge pump/loop
filter.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

The XOR PD will output a 50% duty cycle pulse train at lock. This is much
more difficult to filter down to pure DC, resulting in modulation of the
VCO, and thus sidebands.

It is no different. Control voltage averaged out of an XOR phase
detector is still from essentially the same finite pulse width. [those
have worked for years without any comments about "spurs"]

The vast difference between an XOR PD and the '44-type PFD is
that the XOR PD is limited to a +/- 90 degree control and can't
tell the loop how to come off of a start-up condition which is way
off to one side of the VCO range or the other. The '44-type PFD
works over +/- 180 degree range and DOES indicate a way-off
VCO signal frequency condition. It will start up safely. In the
old PDs limited to 90 degree range, the general way of starting
up was with a very slow sawtooth generator algebraically adding
to the control voltage...once the lock range was achieved, more
circuitry shut off the sawtooth. [lots of extra parts]

In either type of phase detector, the amount of reference frequency
ripple out of the loop filter is dependent on the type of filter and
the
speed of lock-in time on changing frequency of the VCO through
the divider setting. On can make the loop filter very slow and cut
the (awful, terrible) spurious sidebands down...and also waste
literal minutes waiting for the PLL to lock in.

Those (awful, terrible) spurs at increments of the reference
frequency are seldom worth worrying about in a PLL with good
shielding and decoupling around the control voltage parts of the
PLL. [the proof lies in tens of thousands of simple PLLs working
all around the globe without worries over "not working" because
their spurious outputs are "too high"]

Len Anderson
retired (from regular hours) electronic engineer person