Home |
Search |
Today's Posts |
|
#1
|
|||
|
|||
In article , "W3JDR"
writes: John, Elsewhere in this thread there seems to have been some debate on the operation of the phase frequency detector. IMHO if the phase detector has a tri-state output then the loop over time must lock with no phase difference between the reference and controlled signals, ie 0 degrees. Theoretically, the edge controlled PFD locks the signal & reference with 0 degrees phase error. When the loop is locked, the output pulses from the PFD are theoretically infinitesimally small. However, neither the PFD chip nor the external charge pump/loop filter are perfect. Any leakage in the charge pump and/or loop filter causes the PFD to continually output wider than normal pulses in order to supply the additional charge current necessary to make up for the current leakage. This results in a non-zero phase error at the PFD inputs. Not quite it. In order to derive a control voltage for the controlled oscillator, the PFD output MUST BE A FINITE WIDTH. In lock, at any frequency increment, the relative phase of the signal and reference is constant, stable, BUT THERE IS ALWAYS A PHASE OFFSET. This is necessary in order to derive the control voltage which keeps the VCO in lock. It's a common misconception to think of phase lock or even phase control as trying to achieve a "zero degree" condition with no phase offset. What is achieved in phase lock is a STABLE, BUT OFFSET, phase relationship between signal and reference frequencies at PFD inputs. The easiest way to prove the condition is to scope an adjustable- frequency PLL at the signal and reference PFD inputs and then the '44-type PFD output into the loop filter. [measure the VCO frequency separately if desired to prove the VCO, if desired] At one locked frequency of the VCO the PFD output is a finite-width pulse at the reference frequency. Change the divider setting for a new VCO frequency and the PFD output has a different pulse width. That can be confirmed by the DC control voltage...one value at the first frequency setting, another value at the second frequency setting. That DC control voltage is, in effect, an average value of the pulse width out of the PFD. I am struggling to understand the comment above that the AD9901 is not suitable for use in frequency synthesizers because of the large spurious sidebands arising from its use. What causes the additional sidebands ? As mentioned, the PFD output pulses approach zero width at lock, making it easier to filter the pulses down to pure DC in the charge pump/loop filter. No. In the '44-type PFD, the output pulses will be zero ONLY if the divided VCO is way off frequency, at one end of the controllable range or the other. IN LOCK the PFD output will ALWAYS HAVE A FINITE PULSE WIDTH at the reference frequency repetition rate. Without that pulse width averaged out there would be NO control voltage to hold the divided VCO within range. The XOR PD will output a 50% duty cycle pulse train at lock. This is much more difficult to filter down to pure DC, resulting in modulation of the VCO, and thus sidebands. It is no different. Control voltage averaged out of an XOR phase detector is still from essentially the same finite pulse width. [those have worked for years without any comments about "spurs"] The vast difference between an XOR PD and the '44-type PFD is that the XOR PD is limited to a +/- 90 degree control and can't tell the loop how to come off of a start-up condition which is way off to one side of the VCO range or the other. The '44-type PFD works over +/- 180 degree range and DOES indicate a way-off VCO signal frequency condition. It will start up safely. In the old PDs limited to 90 degree range, the general way of starting up was with a very slow sawtooth generator algebraically adding to the control voltage...once the lock range was achieved, more circuitry shut off the sawtooth. [lots of extra parts] In either type of phase detector, the amount of reference frequency ripple out of the loop filter is dependent on the type of filter and the speed of lock-in time on changing frequency of the VCO through the divider setting. On can make the loop filter very slow and cut the (awful, terrible) spurious sidebands down...and also waste literal minutes waiting for the PLL to lock in. Those (awful, terrible) spurs at increments of the reference frequency are seldom worth worrying about in a PLL with good shielding and decoupling around the control voltage parts of the PLL. [the proof lies in tens of thousands of simple PLLs working all around the globe without worries over "not working" because their spurious outputs are "too high"] Len Anderson retired (from regular hours) electronic engineer person |
Reply |
Thread Tools | Search this Thread |
Display Modes | |
|
|
Similar Threads | ||||
Thread | Forum | |||
Phase differences in direct conversion receivers | Homebrew | |||
V and I not in phase at resonance Frequency in RLC network? | Homebrew |