In article , "W3JDR"
writes:

Wrong on all counts Len!

Not quite it. In order to derive a control voltage for the controlled
oscillator, the PFD output MUST BE A FINITE WIDTH.
In lock, at any frequency increment, the relative phase of the signal
and reference is constant, stable, BUT THERE IS ALWAYS A
PHASE OFFSET. This is necessary in order to derive the control
voltage which keeps the VCO in lock.

In the digital PFD, there are essentially two outputs that drive the charge
storage circuit; "pump up" and "pump down". If there is a phase error, the
corresponding output produces pulses that are exactly proportional to the
time-error between the two PD inputs. If the time error corresponds to a
leading phase relationship between VCO and reference, then the "pump down"
output produces pulses equal in width to the lead time, discharging the
charge storage element. If there is a lagging relationship, then the "pump
up" output produces produces pulses equal in width to the lag time, charging
the charge storage element. If there is no error , then neither pump output
produces any pulses, and the charge storage element just 'holds' the last
charge it had on it.

Going to make it one of those long days? :-)

OK, so where is the VCO control voltage coming from and how does
it "know" how to reach the right voltage for the right frequency?

It doesn't...because the PFD output (MC4044 type) does not have
to. There will ALWAYS be a small error in any control loop...
otherwise a control loop couldn't function to do controlling (basic
control loop theory which so many seem to forget).

A "charge pump" is basically a voltage-to-current converter to
develop a basically-DC control voltage for the VCO of the PLL
after the loop filtering. One doesn't need to use the charge
pump in the MC4044 or the 11C44 chip. The digital output of
the PFD can go direct to the loop filter. Even with the charge
pump in-use, the whole thing (pump and loop filter or integrator/
filter) simply integrates a time variation (width of repetitious
pulses out of PFD) into a stable DC value.

In a practical PFD implementation, it is impossible to
maintain the zero pulse-width point because the PFD is a digital feedback
circuit, and you would need parts with zero propagation delay to make such a
circuit.

Absolutely not. There must be SOME gate delay. If there were
zero, then every single D or J-K flip-flop would not work! Since
they do work, there is always SOME internal gate delay.

That internal IC capacitance causing the delay is the cause for all
that heat-dissipation effort on hundred-thousand-plus transistor
junction ICs used in single-chip microcomputers. In a 9- or 10-gate
IC there isn't a lot of heat rise...but the parasitic gate structure
capacitance is always there and all gates have finitie propagation
delays.

Some number of years ago I went into the old databooks (so far
back they were free for anyone and still had the equivalent circuits
in them...like thirty plus years ago) and started doing timing
diagrams to see EXACTLY how they worked. Most interesting bit
of "reverse engineering" and also quite interesting.

The '44-type PFD digital part is essentially a very complex D FF
like structure and it triggers only one direction of transition edges
(like the Ds and J-Ks). The '44 is more complex in trying to see
how it works due to the various conditions of relative input phases.
If there are more than two signal edges for every reference edge,
the outputs hold at one state indicating a "way-off" towards the
high frequency range end of the signal. If there are more than
two reference edges for every signal edge, the outputs flip to the
other state...the "way-off" signal frequency is too low.

However, when there is one input edge for each other input edge,
the outputs produce a variable-width pulse, repetition rate equal
to the reference frequency, which corresponds to the relative
phase of the two inputs. The outputs are always "flipping" when
the inputs are at the same frequency even though the inputs
need NOT be in exact phase positioning. Not a problem. That
variable width turns out to be extremely good for control since a
simple integrator can convert the variable time into a variable
voltage whose DC value is proportional to the relative inputs
phase displacement.

An op-amp integrator circuit functions as a sort of time-to-current-
to-output-voltage converter (technically, the input R is creating a
pseudo-constant-current source for the mid-point of R and C of
the integrator op-amp input). That can also be used as a "Type 1"
loop filter. With some modifications of a basic integrator, it
can become any of the other types. Or, one can, with a sensitive
control voltage characteristic of the VCO, use a passive loop
filter with the filter input directly on the PFD output (choose either
one to go with polarity of the VCO control needed). For that
alternate condition, the PFD Vcc *MUST* be stable and decoupled
less it mess around with more badness in the control voltage.
The "charge pump" circuit of the MC4044/11C44 is really optional
to use. It isn't absolutely necessary although it can cut down on
the number of parts used.

Based on hands-on observation of several of these PLLs, especially
those of PFDs made from individual logic gates, the PFD outputs
ARE pulses at the reference frequency repetition rate. Their width
is proportional to the integrated-averaged DC control voltage of the
VCO when in lock.

If what you say is true, then there would be ZERO control voltage
out of any of the mentioned interface circuits. Obviously, there
must be some finite amount of control voltage for the VCO to
adjust to a particular PLL frequency increment. That control
voltage is the integrated-averaged DC out of the loop filter, not
some mythical "charged whatsis" from that charge pump.

In looking at the relative phases of the signal and reference AC
inputs, the loop is LOCKED even though the phases are
offset. The phases remain "in step" and unchanging on the
'scope but they are offset in phase from one another. [that's
normal with this kind of PFD and PLL] I've been looking at
these things for about three decades and see the same things.
With the MC145151 combo PLL chip I'm playing with now, the
PFD gates aren't fully available for peeking, but it locks in as
advertised as I said above.

However, the width of the pulses in modern designs can get down
into the nanosecond range at lock.

Nobody, not even the PLL really cares. How much voltage are
you going to generate on the VCO control line from nanosecond
pulse widths at a 1 KHz reference input repetition rate? Very
little.

For this reason, the PFD can produce much
lower sideband content than the XOR, which outputs large pulses at lock. The
larger the output pulse, the more difficult the loop filter design.

The only thing "difficult" about a PLL is others paying attention to
the REQUIRED values of control voltage gain and the reference
frequency AND the simple math needed to calculate those values.
"Difficult" is when the control voltage isn't linear over frequency
(which upsets the heck out of the control gain at one end of the
VCO range). "Difficult" is not paying attention to the subcircuit
isolation and shielding and decoupling that produces the control
voltage where it is ripe for picking up garbage that results in all
kinds of badness in VCO stability.

No. In the '44-type PFD, the output pulses will be zero ONLY if
the divided VCO is way off frequency, at one end of the controllable
range or the other. IN LOCK the PFD output will ALWAYS HAVE
A FINITE PULSE WIDTH at the reference frequency repetition rate.
Without that pulse width averaged out there would be NO control
voltage to hold the divided VCO within range.

Wrong again! With large frequency errors, the PFD produces constant pumping.
If it didn't, it couldn't acquire with phase errors larger than 180deg.

No. If you examine the states of all gates in a '44 PFD with
corresponding input waveform states, you will see that the
"way-off" (phase errors larger than 180 degrees) conditions of
the PFD outputs REMAIN in their fully-on or fully-off states.
That's the gem of this gate arrangement and the key to coming
into lock on power-up.

One reason I submitted my article to Jim Fisk at Ham Radio
magazine (it was not in the original sequence at the start of that
series) was as a result of trying to explain the gate-states of the
'44 PFD to another. The waveform timing diagrams in that
September 1982 article accurately show the state changes
(without the precise amount of internal gate delay, not really
needed in explanation). Just to make certain, I'd duplicated the
gate logic in an Apple ][ program to make sure...and to see the
variations in original conditions that might cause a bad start-up.
I didn't use the conventional bubble-and-arrow state change
diagrams since so few contemporaries could "read" them and
I didn't much care for that kind of presentation either. Waveforms
were an old familiar thing and I stuck with that.

You are also wrong in asserting that the lock-in range of the PFD is +/- 180
degrees. In fact, it is infinite (in theory).

"Infinite" only in the grossest sense of being - in effect - locked
up on either of the "way-off" conditions. From what I gather, it
was designed to do that very thing. An excellent thing to insure
start-up.

However, integrated-averaged to DC, the outputs of the PFD make
an excellent phase meter with a DC that can be converted to
binary in an A-to-D. The Rocketdyne Deformable Mirror project
used that characteristic to measure the heterodyned optical
signals from the optics at 1 MHz PFD input. It worked just fine
out to about +/- 179 degrees or so when calibrated for the whole
optical-electronic loop. [optics could approach 180 but never
quite get exactly there...but then that's difficult with electronics
also, needing time-interval averaging counters and such which
we DID use...but the optics folks wanted to tweak their stable
table optics more than tweaking instrument dials...:-)]

Yes, its linear output
compliance range is +/- 180 degrees, but it can acquire lock even when there
is an infinite frequency error. This is because once the PFD output exceeds
it's compliance range, it outputs a constant "pump up" or "pump down" pulse
train, which in turn causes the loop filter voltage to ramp up or down as
the case might be until the signal comes back into the compliance range and
lock is established.

No. At beyond-control-range input frequencies, the PFD outputs
go to their stable, unchanging "way-off" states and stay there
until both inputs are the same frequency. Ain't no "pump" pulses
whatsoever at those "way-off" conditions.

The XOR's big advantage is that it is simple, and there is no discontinuity
around the phase lock point (as there is in the PFD), but it does not lock
up readily in the face of frequency errors. The PFD's advantage is that it
readily locks up, even in the face of large frequency errors and it also
produces an easily filtered output.

In practice, since the last days of WW2, phase-frequency control
loops have used lots of extra circuitry to cure that start-up. Philco
did that with some S-band microwave radio relay gear used by the
USAF in 1955. Army used L-band crystal-controlled microwave
radio relay terminals by GE, had no problems. USAF had Philco
tech reps there seemingly all the time since their frequency control
tended to pop off lock and go sweeping frequency a lot from their
extra sawtooth circuitry. [PLL was first disclosed in 1932 by
"H. de Bellecize, working in France" according to my giant
1980 50th anniversary special edition of Electronics magazine]

There have been a few PFD circuits devised before the '44 type
but I'd say the '44 went all the way to excellence with elegance
in its simplicity. There have been at least one close to the '44
but arranged differently and with more internal parts...but that one
works about the same as the '44.

When you get the chance, grab a 'scope and look into the
waveforms of a PFD as well as the control voltage. You will
find out I'm right. No "theory" on that, just working PLL
hardware. I've seen and observed that, used the basic
knowledge to build my own PLLs (including a couple just for
me) and am confident in the explanation I gave. They WORK
by all the nice instruments from Hewlett and Packard (rest
their souls).

Len Anderson
retired (from regular hours) electronic engineer person