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			Hi! 
		
		
		
		
		
		
		
		
	
	I need help understanding a conventional phase/frequency detector.I consists of 6 two input NAND gates and 3 three input NAND gates.It compares the phase and generates UP and DOWN signals.I was wondering why the dead zone is high specially when there is a large reset delay path. Deepthi  | 
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