the crucial piece of information is that noise stays even when you
have opened up the VCO loop.

looking at your setup, it appears to me that the noise can come from
two sources, a) the VCO and b) the PLL. evidentaly, it is not from the
VCO as your experiments prove. it is probably from the PLL circuitry.
this is quite possible. the PLLs involve a lot of digital, noisy
switching that can generate these birdies and spurs. however, these
should stay well inside the PLL block. in your case, they are getting
coupled back to your output.

there are a number of cures for this. all of them will work at a
better buffer between the vco and the following PLL. the simplest
solution is use a grounded gate FET amplifier between the PLL input
and the VCO output. be careful though, such a configuration is almost
gaurenteed to self oscillate. but that is easily taken care of. what
you do is this .. solder the FET upside down with its legs sticking
up. solder the gate to the ground with as small a lead as you can.
then, using a thin copper sheet or an unetched pcb, make a sheild that
is soldered vertically over the FET (with a cutaway to allow the FET
body). keep the source and drain leads on opposite sides of the
sheild. bias the FET for nominal current at about half the Idss.

if you have a copy of EMRFD around, you can check this design in the
chapter on oscillators.

- farhan

all of them will work at a
better buffer between the vco and the following PLL. the simplest
solution is use a grounded gate FET amplifier between the PLL input
and the VCO output. be careful though, such a configuration is almost
gaurenteed to self oscillate. but that is easily taken care of. what
you do is this .. solder the FET upside down with its legs sticking
up. solder the gate to the ground with as small a lead as you can.
then, using a thin copper sheet or an unetched pcb, make a sheild that
is soldered vertically over the FET (with a cutaway to allow the FET
body). keep the source and drain leads on opposite sides of the
sheild. bias the FET for nominal current at about half the Idss.

Yes, that also sounds for me the best thing to do (improving buffer
between VCO and PLL). Well, I'm not experienced with such circuits, so
could you just explain how to bias the FET.


VCO o-||-- S-D --||--o OUT TO PLL
^ FET=MPF102 or stg like that
G
|
o----------------o GND


And one last thing, could you re-explain how you advise to shield the
FET ? I don't see what you mean :-(

Thanks for your answer ;-)

If anyone else has got the answer, come on, post !

Yes, that also sounds for me the best thing to do (improving buffer
between VCO and PLL). Well, I'm not experienced with such circuits, so
could you just explain how to bias the FET.


VCO o-||-- S-D --||--o OUT TO PLL
^ FET=MPF102 or stg like that
G
|
o----------------o GND


And one last thing, could you re-explain how you advise to shield the
FET ? I don't see what you mean :-(

Thanks for your answer ;-)

(Damien Teney) wrote in message . com...

And one last thing, could you re-explain how you advise to shield the
FET ? I don't see what you mean :-(

Thanks for your answer ;-)

let me explain this a little more visually.

to begin with, i imagine that you are building this ugly style over a
copper clad board. Now, imagine that you have soldered another piece
of copper clad board (about an inch high and 2 inches across) so that
stands vertically at ninety degrees from the base board.
Now imagine that you have cut out a small mouse hole in this 'wall'.
The size of the mouse hole is just enough to let the FET's body (and
not the leads) pass through.
You take an FET, bend its drain and source to ninety degrees and away
from the FET body. Now you slide the FET into the mouse hole. Bend
down the gate and solder it to the base copper clad board.The source
and drain leads should be on either sides of this wall (the sheild).
this will prevent the source and drain from coupling the energy back
to each other.

- farhan

In article ,
Ashhar Farhan wrote:

let me explain this a little more visually.

to begin with, i imagine that you are building this ugly style over a
copper clad board. Now, imagine that you have soldered another piece
of copper clad board (about an inch high and 2 inches across) so that
stands vertically at ninety degrees from the base board.
Now imagine that you have cut out a small mouse hole in this 'wall'.
The size of the mouse hole is just enough to let the FET's body (and
not the leads) pass through.
You take an FET, bend its drain and source to ninety degrees and away
from the FET body. Now you slide the FET into the mouse hole. Bend
down the gate and solder it to the base copper clad board.The source
and drain leads should be on either sides of this wall (the sheild).
this will prevent the source and drain from coupling the energy back
to each other.

A slight variation on this approach, which I've seen recommended for
use with U310 (TO-52 metal case) is to actually drill a small hole
downwards through the "ugly-style" copperclad, just barely large
enough to admit the body of the JFET. Drop the JFET into the hole -
it's fine if the metal case contacts the copper, as the case and gate
are connected together. Bend the source and drain out sidewise, leave
the gate lead sticking up in the air, put the shielding piece of
copperclad with the "mouse hole" into place, solder it to the board,
and then solder the gate lead to the copperclad on one side of the
shield.

This results in a very short, low-inductance connection of the gate to
ground.

This technique would probably work just about as well with a J310 or
similar TO-92 plastic-package JFET, although it won't give the
additional benefit of grounding/shielding via the metal case.

As to the U310 - anyone know of a convenient source? I haven't seen
anyone selling old-stock U310s on the Net, and there's only one
manufacturer I know of making them (Linear Systems).

--
Dave Platt AE6EO
Hosting the Jade Warrior home page: http://www.radagast.org/jade-warrior
I do _not_ wish to receive unsolicited commercial email, and I will
boycott any company which has the gall to send me such ads!

Thanks I've understood what you mean ;-)

bias the FET for nominal current at about half the Idss.

As I'm not (yet) familiar with such circuits, so could you tell me how to do
this :-$ ? Thanks.

Damien

"Damien Teney" wrote in message ...
Thanks I've understood what you mean ;-)

bias the FET for nominal current at about half the Idss.

As I'm not (yet) familiar with such circuits, so could you tell me how to do
this :-$ ? Thanks.

Damien

W7ZOI has a quick and dirty way of finding this out.
1) Connect a 1K resistor from the drain of the FET to 12v power
supply.
2) solder a 10K resistor from the source of the FET to ground.
3) ground the gate
4) apply power and measure the voltage on the source. this gives you
the pinchoff voltage (Vp).
5) short the source to the ground as well. Meausre the current flowing
through the drain (you can measure the voltage between the drain and
the 12v supply and divide it by 1000). This current value is IDss.

Now, choose a source resistor of the value Vp/(Idss * 4).

btw, you can simpley chuck all this and try 560 ohms. it should work
. the gain, noise figure etc are not too crucial. the idea is to
buffer the input and output.

- farhan

- farhan

Okay, but that stuff is only used to find out the Vp and Idss I guess ?
So the "amplifier" itself is only made up of the FET, with the gate
grounded, the drain as output, and the source as input via 1 resistor (560
ohms) ?

Damien

PS: that's probably the last question ;-)

W7ZOI has a quick and dirty way of finding this out.
1) Connect a 1K resistor from the drain of the FET to 12v power
supply.
2) solder a 10K resistor from the source of the FET to ground.
3) ground the gate
4) apply power and measure the voltage on the source. this gives you
the pinchoff voltage (Vp).
5) short the source to the ground as well. Meausre the current flowing
through the drain (you can measure the voltage between the drain and
the 12v supply and divide it by 1000). This current value is IDss.

Now, choose a source resistor of the value Vp/(Idss * 4).

btw, you can simpley chuck all this and try 560 ohms. it should work
. the gain, noise figure etc are not too crucial. the idea is to
buffer the input and output.

- farhan

Thank you Ashhar, your tip was the best :-) I've added a grounded gate FET
between the VCO and the PLL and now the receiver works as well with as
without the PLL circuit. I still have to adjust the loop filter because it
is not perfect; it can lock on the right frequency and keep it but the
output voltage of the filter doesn't look clean enough on the scope.

Thanks everybody for your advises, and cya ;-)

Damien