In article ,
Fred Bloggs wrote:


John Larkin wrote:


Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John


Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.


--
--
forging knowledge