The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
or a little more if it's high-Z. The output of the device under test
has a transformer and then a series cap to create an unbalanced output.


I did something ugly with a 3.3v cmos 7406 varient and a feedback
resistor, which works well enough to get an accurate reading on one
version of the device under test, but not on the other (both have been
verified with real test equipment) It also tends to self-oscillate
with no input...

What would be the right way to do this using on hand parts, such as
abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to
use another gate with a feedback resistor and cap to ground in the hope
of establishing the threshold level, and then using a transformer to
swing another input above and below this. Most parts on hand are SMD -
which means dead bug construction in SOIC scale under the maginifier -
discourages extensive experimentation.

Why do most abuse-of-logic RF applications seem to use NAND gates
rather than inverters? From a digital perspective NAND gates are a
universal element, but once you tie their inputs together, is there
something to be gained from having two inputs in parallel?

Is there a way to use a differential input configuration on an FPGA to
input a balanced RF signal directly? Theoretically this should be an
FPGA clock input... The device in use currently is an Altera Stratix
II, but a Xilinx S3 kit is available.

If ordering things, what would be a good default low supply voltage
HF/VHF gain component to have on hand? I seem to recall lots of
last-millenium ham designs using the MC1350P video IF amp, but what
would make sense today?

wrote:
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

Does the FPGA have LVDS option inputs ?
If it is new enough to have those, they are differential
amplifiers, designed for current mode signals, and will work
with thresholds 1V.
IIRC the LVDS spec has +100mV and -100mV levels.
Normally, they need a common mode bias of just over 1V, and the
better ones will also tolerate rail-rail drive (on ONE ip),
but at reduced speed specs.
-jg

On Thu, 23 Feb 2006 16:23:13 +1300, Jim Granville
wrote:

wrote:
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

Does the FPGA have LVDS option inputs ?
If it is new enough to have those, they are differential
amplifiers, designed for current mode signals, and will work
with thresholds 1V.
IIRC the LVDS spec has +100mV and -100mV levels.
Normally, they need a common mode bias of just over 1V, and the
better ones will also tolerate rail-rail drive (on ONE ip),
but at reduced speed specs.
-jg

Second that. We've tested the Xilinx Spartan3 LVDS inputs and they are
excellent, super-fast comparators.

John

For gain, have a look at MMICs. Minicircuits sell them in kits that
give you a good range of performance. They're easy to use, and run on
a single supply.

I think the idea of using the LVDS inputs on the FPGA is a good one, if
you can get that into the clock lines you need to use. Otherwise, you
only need a little gain to get to levels you need for logic input. Do
your clock input lines have a bit of hysterisis? Do they have high
enough input impedance to be used with a step-up transformer? Can you
reliably bias the transformer DC return to a point between the
hysterisis trip-points. I suspect you can do a better job with your
logic-gate amplifier, too. Or you could make a fancier input using one
of the very fast comparators.

Cheers,
Tom

As Jim has said LVDS is a good way. Just watch the common mode input range.
You can use a RF transformer to rebias the DC level to get arround any
issues.

Another way is to use a single ended standard like SSTL and DC bias the
input to the reference voltage used for the SSTL. You do need to have access
to Vref pins on the Spartan-3 to use this technique.

We have support for LVDS and SSTL in our boards but I am not sure about the
Spartan-3 starter kit.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The low Cost Spartan-3 Development
Board.
http://www.enterpoint.co.uk

wrote in message
oups.com...
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
or a little more if it's high-Z. The output of the device under test
has a transformer and then a series cap to create an unbalanced output.


I did something ugly with a 3.3v cmos 7406 varient and a feedback
resistor, which works well enough to get an accurate reading on one
version of the device under test, but not on the other (both have been
verified with real test equipment) It also tends to self-oscillate
with no input...

What would be the right way to do this using on hand parts, such as
abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to
use another gate with a feedback resistor and cap to ground in the hope
of establishing the threshold level, and then using a transformer to
swing another input above and below this. Most parts on hand are SMD -
which means dead bug construction in SOIC scale under the maginifier -
discourages extensive experimentation.

Why do most abuse-of-logic RF applications seem to use NAND gates
rather than inverters? From a digital perspective NAND gates are a
universal element, but once you tie their inputs together, is there
something to be gained from having two inputs in parallel?

Is there a way to use a differential input configuration on an FPGA to
input a balanced RF signal directly? Theoretically this should be an
FPGA clock input... The device in use currently is an Altera Stratix
II, but a Xilinx S3 kit is available.

If ordering things, what would be a good default low supply voltage
HF/VHF gain component to have on hand? I seem to recall lots of
last-millenium ham designs using the MC1350P video IF amp, but what
would make sense today?

I did something ugly with a 3.3v cmos 7406 varient and a feedback
resistor, which works well enough to get an accurate reading on one
version of the device under test, but not on the other (both have been
verified with real test equipment) It also tends to self-oscillate
with no input...

7406 is open collector. Did you mean 7404?

What size feedback resistor? What sort of oscillations?

I've had reasonable luck with that sort of hacking. Not great.

What's the output of your gate look like? Is it cleanly switching
or struggling to switch at that speed?

You might want to skip the external gate and use an inverter
in the FPGA out to a feedback pin. That gets the feedback
covering the input pin that you are really interested in.


--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

wrote:

The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
or a little more if it's high-Z. The output of the device under test
has a transformer and then a series cap to create an unbalanced output.


I did something ugly with a 3.3v cmos 7406 varient and a feedback
resistor, which works well enough to get an accurate reading on one
version of the device under test, but not on the other (both have been
verified with real test equipment) It also tends to self-oscillate
with no input...

What would be the right way to do this using on hand parts, such as
abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to
use another gate with a feedback resistor and cap to ground in the hope
of establishing the threshold level, and then using a transformer to
swing another input above and below this. Most parts on hand are SMD -
which means dead bug construction in SOIC scale under the maginifier -
discourages extensive experimentation.

Why do most abuse-of-logic RF applications seem to use NAND gates
rather than inverters? From a digital perspective NAND gates are a
universal element, but once you tie their inputs together, is there
something to be gained from having two inputs in parallel?

the only gain is some PWB layout simplifications and less wasted part
sections.


Is there a way to use a differential input configuration on an FPGA to
input a balanced RF signal directly? Theoretically this should be an
FPGA clock input... The device in use currently is an Altera Stratix
II, but a Xilinx S3 kit is available.

If ordering things, what would be a good default low supply voltage
HF/VHF gain component to have on hand? I seem to recall lots of
last-millenium ham designs using the MC1350P video IF amp, but what
would make sense today?

I am thinking on the order of a single transistor amplifier to go to logic
levels, then characterize it for delay issues.
--
JosephKK
Gegen dummheit kampfen Die Gotter Selbst, vergebens.
--Shiller

... but what
would make sense today?


http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

Fred Bloggs wrote:
... but what
would make sense today?


http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

That sounds like a good idea, because theoretically we actually have
some on hand somewhere, I'll have to see if I can scare them up.

While connecting to the FPGA directly would be simpler, I do like the
idea of using an external chip as a bit of a 'fuse'. (Though
transformer coupling into the FPGA should reduce some risk)

wrote:
Fred Bloggs wrote:
... but what
would make sense today?


http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

That sounds like a good idea, because theoretically we actually have
some on hand somewhere, I'll have to see if I can scare them up.

Found one and wired it up as the datasheet suggests - cap coupled input
to half the differential pair, the other side floating at the reference
output pin voltage with decoupling cap to ground, terminating resistor
across the pair. Worked quite well.

The xilinx S3 kit from digilent doesn't seem to be designed with using
the differential input capability as the pairs are split up all over
the place. Not certain that I couldn't bias one input of a pair as a
reference wherever it is and drive the other pin wherever that is, but
putting it all in a little package seemed simpler.