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Old June 13th 06, 03:16 PM posted to rec.radio.cb
 
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PowerHouse Communications schreef:

"Jan Panteltje" wrote in message
...

I did a nice frequency counter on an FPGA lab board:
http://panteltje.com/panteltje/fpga/...nter-0.2.1.bz2


And just how do you open/view such a beast? WinRAR opened the file, but
left me with another file that was unknown and completely useless... If you
are trying to make a point, you might want to put it in a format that humans
can actually use...


'bz2' is a compressed format, it is open source, and frequently used in
Linux.
It has a higher compression ratio then for exmpel 'zip' or tgz.
the correct way to 'unpack' it in Linux / unix is:
tar -jxvf frequency_counter-0.2.1.bz2
In MS windows there is as far as i knwo no correct way to do anything,
so I
cannot help you there.
You would only find verilog source files anyways, and then complain you
cannot read verilog (language), that posting really was on level3, you
were still on level 1.

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Old June 13th 06, 04:39 PM posted to rec.radio.cb
PowerHouse Communications
 
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wrote in message
oups.com...

PowerHouse Communications schreef:

"Jan Panteltje" wrote in message
...

I did a nice frequency counter on an FPGA lab board:
http://panteltje.com/panteltje/fpga/...nter-0.2.1.bz2


And just how do you open/view such a beast? WinRAR opened the file, but
left me with another file that was unknown and completely useless... If

you
are trying to make a point, you might want to put it in a format that

humans
can actually use...


'bz2' is a compressed format, it is open source, and frequently used in
Linux.
It has a higher compression ratio then for exmpel 'zip' or tgz.
the correct way to 'unpack' it in Linux / unix is:
tar -jxvf frequency_counter-0.2.1.bz2
In MS windows there is as far as i knwo no correct way to do anything,
so I cannot help you there.


Like I told you, WinRAR opened (uncompressed) the file (unpack[ed] it in
your language)...

You would only find verilog source files anyways, and then complain you
cannot read verilog (language), that posting really was on level3, you
were still on level 1.


I could really give a **** less what planet you are on, I asked a simple
question, all you had to do was answer it without your nasty attitude.

It was nice of you to provide a link, however I'd roughly guess that over
98% of the people reading this group, including the person you replied to,
does not use Linux, and therefore would have no use for the file. Oh, and
since you have a cocky attitude about you, let me return the favor... IT'S
"example", NOT "exmpel"!


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Old June 13th 06, 09:04 PM posted to rec.radio.cb
Jan Panteltje
 
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On a sunny day (Tue, 13 Jun 2006 10:39:49 -0500) it happened "PowerHouse
Communications" wrote in
:

You would only find verilog source files anyways, and then complain you
cannot read verilog (language), that posting really was on level3, you
were still on level 1.


I could really give a **** less what planet you are on, I asked a simple
question, all you had to do was answer it without your nasty attitude.

It was nice of you to provide a link, however I'd roughly guess that over
98% of the people reading this group, including the person you replied to,
does not use Linux, and therefore would have no use for the file. Oh, and
since you have a cocky attitude about you, let me return the favor... IT'S
"example", NOT "exmpel"!


Yea, but we were actually playing a game, although you may not have known
when you dropped into to it.

The issue of the game is to 'up the tech level' the top level is unlimited.

Verilog, as hardware description langue is not bound to any OS.
It is just a text format to describe how gates and other logic is connected
in a chip.

Somebody else has already explained how to unpack that file on a Billy Gates
OS.

Yea the spelling, often lots of data distortion from this planet.
noise, cracks... sssssssssssssssssssssssssssss
grin




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Old June 14th 06, 05:36 PM posted to rec.radio.cb
PowerHouse Communications
 
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"Jan Panteltje" wrote in message
...
On a sunny day (Tue, 13 Jun 2006 10:39:49 -0500) it happened "PowerHouse
Communications" wrote in
:

You would only find verilog source files anyways, and then complain you
cannot read verilog (language), that posting really was on level3, you
were still on level 1.


I could really give a **** less what planet you are on, I asked a simple
question, all you had to do was answer it without your nasty attitude.

It was nice of you to provide a link, however I'd roughly guess that over
98% of the people reading this group, including the person you replied

to,
does not use Linux, and therefore would have no use for the file. Oh,

and
since you have a cocky attitude about you, let me return the favor...

IT'S
"example", NOT "exmpel"!


Yea, but we were actually playing a game, although you may not have known
when you dropped into to it.


Nope, wasn't aware of that, thanks for filling me in...

The issue of the game is to 'up the tech level' the top level is

unlimited.

Verilog, as hardware description langue is not bound to any OS.
It is just a text format to describe how gates and other logic is

connected
in a chip.


So, if I were to try "viewing" this in a text editor, I should be able to
see it? Let try...

I see where I had a problem... The decompressed file needed to be
decompressed as well. Now the folder shows it's face, with all files
within... I jumped the gun too soon... Got it now.. TAR archive
within a BZIP2 archive...


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Old June 14th 06, 09:33 PM posted to rec.radio.cb
Jan Panteltje
 
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On a sunny day (Wed, 14 Jun 2006 11:36:59 -0500) it happened "PowerHouse
Communications" wrote in
:
So, if I were to try "viewing" this in a text editor, I should be able to
see it? Let try...

I see where I had a problem... The decompressed file needed to be
decompressed as well. Now the folder shows it's face, with all files
within... I jumped the gun too soon... Got it now.. TAR archive
within a BZIP2 archive...


OK, I will explain a bit... if you look with the text editor at the file
'top.v' you will first see 'module top'
think of a module as an electronic digital circuit.

The top module is like a big diagram that is made up of all these separate
circuits, other modules, like for example 'lcd_text_driver', 'b2bcd0',
'txua0', all separate diagrams.

In this case nothing is analog, so no AD DA conversions.

You will see 'wire' for exactly what it is, wires that connect things,
OBUF IOBUF for digital buffers, and 'reg' for a register, basically one
or more flipflops....

If circuits get very large, diagrams quickly become unreadable
and difficult to modify.
Languages like Verilog make it easy to maintain and design large complicated
digital circuits, and are portable across many platforms (schematic editors
are not).
In an FPGA (Field Programmable Gate Array) many CMOS switches are used
to connect all sorts of logic blocks together.
There exist (free) programs that read the Verilog text files, create
a binary file for some FPGA chip, that you can then program into such a chip,
and the chip will set the switches, your Verilog design will be created
in the chip *without you soldering one single connection*.
The Spartan2 FPGA I used has has the equivalent of some 200,000 logic gates,
so quite a lot can be done.
There are many free projects look for example he
http://www.opencores.org/browse.cgi/by_category

http://www.fpga4fun.com/

There are many of those prototype boards, best get one with VGA connector
and audio stuff, the relevant newsgroup is comp.arch.fpga.
But it is only limited by ones own imagination....

So that was some more ...
Will throttle back a bit now and see what he effect of this is.....








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Old June 14th 06, 10:27 PM posted to rec.radio.cb,rec.radio.amateur.policy
James Crow
 
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"Jan Panteltje"

SNIP

Jeeze...jan......you're such a bore!



--
Posted via a free Usenet account from http://www.teranews.com

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Old June 14th 06, 10:29 PM posted to rec.radio.cb,rec.radio.amateur.policy
an old freind
 
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Default get help


James Crow wrote:
"Jan Panteltje"

SNIP

Jeeze...jan......you're such a bore!

why do you find it desriable to spread out your filth over another NG

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Old June 14th 06, 10:44 PM posted to rec.radio.cb
DrDeath
 
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"James Crow" wrote in message
...
"Jan Panteltje"

SNIP

Jeeze...jan......you're such a bore!


I guess it is boring when you are unable to comprehend the subject matter.
Don't you have trolling to do on RRAP?


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