Hi John,

The BF537 EZ-KIT Lite + AD7763 for less than US$180 looks like a
brilliant deal to me, but won't you need I as well as Q channel ADCs ?

I am not sure how much enthusiasm I can muster for a BF537 when only
packaging available is 192 or 208 BGA, it sounds like a project that
is always destined to be a prototype board. It does look like a very
capable DSP however.

If you want to experiment with SDR, does it get any simpler than
SoftRock 40 ? I guess I have a natural inclination to use a platform
where there is an established user base - hence plenty of help and
support.

My other inclination is also to try and keep the sample rate as low as
possible, so there are plenty of un-optimized-code CPU cycles
available to allow swift algorithm development rather than scrambling
around for every last CPU cycle at the start of a project.

Having said that all out loud, my inclination is to go for a decent
DDS LO, for front end agility, sampling down to a high sample rate
(192kHz) stereo (I + Q) audio ADC and to take it from there in DSP.

With that all under my belt, then time to look at higher performance
solutions, once the question is better understood.

Regards,

Mark



On Jul 1, 11:57 am, wrote:
I'm trying to get an idea of some of the tradeoffs involved in
determining
where to perform the analog to digital conversion for a SDR design
which
uses 200 MHz as the first IF (pick due to SAW filter availability and
it's
high enough to simplify the front end filter bank ... the receiver is
a
homebrew type intended to cover .5 - 600 MHz with a maximum signal
bandwidth of 200 kHz).

Some options:

1) Sample at the first IF using subsampling.

Advantages: Eliminates the need for an additional LO and mixer.

Disadvatages: Brad Evans points out in a comp.dsp article entitled
"Undersampling (was: RF/IF digital receiver)" that using a high IF
means that it will be more sensitive jitter in the ADC clock.

The LTC2203 does 25 Msps with a 16 bit output and has a front end
which
can handle 380 MHz.

The AD7763 does 40 Msps with a 24 bit output and includes a digital
FIR.
However, it's not clear to me what's the maximum frequency that it
can handle.
What's very interesting is that Analog Devices has an evaluation
kit
(EVAL-AD7763) available from Digikey for only 163 dollars and it
includes (according to the literature) a BF537 EZ-KIT Lite. This
appears
to be a very inexpensive way to experiment with SDR.

2) Convert the first IF to a second IF of 21.4 MHz and then subsample.

Advantages: Less sensitive to ADC clock jitter. Many different
crystal
filter are available for 21.4 MHz from places such as Network
Sciences.
This allows additional filtering to be done in the analog domain
which
should increase sensitivity.

Disadvantages: Involves an additional LO and mixer which means more
noise.
ADSimPLL says the LO noise is -114 at 10 kHz. Mixer spurs at 7x8
and 8x9.
I'm assuming that the spurs are not that interesting given I'm
using a LT5512
which is a double balance mixer (i.e. even harmonics don't occur).

I imagine that the AD7763 will handle subsampling 21.4 MHz.

3) Convert the second IF to a third IF of 2.9 MHz and sample using a
AD9874.

Advantages: The AD9874 also contains AGC and an I/Q demodulator in
addition
to a LO PLL and mixer. This means that the DSP doesn't have to
handle these
chores.

Disadvantages: Involves an additional LO and mixer which means more
noise.
ADSimPLL says the LO noise is -119 at 10 kHz. Mixer spurs at 6x7,
7x8, and
8x9. I'm assuming that the spurs are not that interesting given
the AD9874
mixer is a double balance type (i.e. even harmonics don't occur).

BTW: I'm willing to sacrifice some performance if it means making the
hardware
easier to build (i.e. allows for more slop in the PC layout and
assembly).

What are peoples thoughts, opinions, and experiences regarding these
types of
tradeoffs?

-- John