In article ,
(Deepthi) writes:

Hi!
I need help understanding a conventional phase/frequency detector.I
consists of 6 two input NAND gates and 3 three input NAND gates.It
compares the phase and generates UP and DOWN signals.I was wondering
why the dead zone is high specially when there is a large reset delay
path.
Deepthi

The "conventional phase-frequency detector" I know is the basic
circuit of the Motorola MC4044 package. That one is explained in
detail - in the form of a timing chart of ALL gate states with little
arrows indicating which gate acts on other gates - in the
September, 1982, issue of HAM RADIO Magazine in the "Digital
Techniques" column titled "Inside A Phase-Frequency Detector
(MC4044)." The particular timing diagram is rather straightforward
waveform diagrams rather than the symbolic logic-state graphics
others have used. I am the author of that column.

The "dead zone" you mention is due to differential gate delays
and can be minimized with high-speed logic families. It has
several causes depending on whether the signal input is leading
or lagging the reference input. The waveform diagram lets you
select either one and, with a schematic, see the path that causes
the differential gate delay.

Len Anderson
retired (from regular hours) electronic engineer person

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

Rick N6RK

"Avery Fineman" wrote in message
...
In article ,
(Deepthi) writes:

Hi!
I need help understanding a conventional phase/frequency detector.I
consists of 6 two input NAND gates and 3 three input NAND gates.It
compares the phase and generates UP and DOWN signals.I was wondering
why the dead zone is high specially when there is a large reset delay
path.
Deepthi

The "conventional phase-frequency detector" I know is the basic
circuit of the Motorola MC4044 package. That one is explained in
detail - in the form of a timing chart of ALL gate states with little
arrows indicating which gate acts on other gates - in the
September, 1982, issue of HAM RADIO Magazine in the "Digital
Techniques" column titled "Inside A Phase-Frequency Detector
(MC4044)." The particular timing diagram is rather straightforward
waveform diagrams rather than the symbolic logic-state graphics
others have used. I am the author of that column.

The "dead zone" you mention is due to differential gate delays
and can be minimized with high-speed logic families. It has
several causes depending on whether the signal input is leading
or lagging the reference input. The waveform diagram lets you
select either one and, with a schematic, see the path that causes
the differential gate delay.

Len Anderson
retired (from regular hours) electronic engineer person

In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

Len - Avery, whomever,
Our experiences differ. When designing PLL synths back then for two-war
radio, we always saw the dead zone. In a type 2 loop (hope I'm remembering
my control theory correctly) the extra integration allows the VCO to float
around within the dead zone, causing a low freq rumble at times. You could
watch the phase wandering around on a scope on the two PD inputs. We would
force some small leakage current just to hold it up against one side of the
dead zone. Perhaps the types of requirements causes the difference. We
were in the audio range with the PD reference freq and lock times in the
tens of ms. if I recall correctly.
If I recall, the Fairchild chip did a better job of matching the delays.
The small overlap causing a narrow pulse to occur seemed like a small
issue - not much energy at the ref freq for some applications. Our
synthesizers were of such requirements that there was a very tight balance
between lock time and spurious. The loop filtering took much care to get
the lock time and keep reference spurs down.
I designed and built what I still believe is the first 2-meter synth hand
held in 1973. 8.0 ma current max drain (varied 'tween 6.5 and 8 across the
band), 70dB spurious (the radio originally was 43 dB). 5kc resolution. In a
Motorola HT-220. Still have it. A year later I got tired of doing the
dip-switches and designed a keyboard entry system. That fella with the
HT-220 site didn't put it on. He does have Dale Heatherington's (sp) though
(got a couple of them also).
--
Steve N, K,9;d, c. i My email has no u's.

In article , "Steve Nosko"
writes:

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

Len - Avery, whomever,
Our experiences differ. When designing PLL synths back then for two-war
radio, we always saw the dead zone.

"Two-war radio?" PRC-25? Term not understood. Experience has
hands-on with everything from a PRC-8 to a PRC-104, but little with
the PRC-25 or -77.

In a type 2 loop (hope I'm remembering
my control theory correctly) the extra integration allows the VCO to float
around within the dead zone, causing a low freq rumble at times. You could
watch the phase wandering around on a scope on the two PD inputs.

If the loop is set for something like a 10 to 50 mSec lock-in time,
one has to look quick to see the actual lock-in. If the loop is
designed properly (VCO control voltage gain, time relative to the
reference frequency), there should not be any "wander."

In order to see the settling time from a large step-function of
frequency change, you need to sync a scope from the step
source and watch the jump-and-settle of the control voltage like
a damped sinewave. That's a quick check of loop control
action. Storage scope (old way) or digital scope (muy better)
are the best way to view that.

We would
force some small leakage current just to hold it up against one side of the
dead zone. Perhaps the types of requirements causes the difference. We
were in the audio range with the PD reference freq and lock times in the
tens of ms. if I recall correctly.

Most of the older PLLs had reference frequencies of 1 to 5 KHz.
That's a period of 1.0 mS to 200 uS. Without about 5 to 10
cycles for settling-in (to near invisibility), that would be about
10 to 2 mS, rather quick.

If I recall, the Fairchild chip did a better job of matching the delays.
The small overlap causing a narrow pulse to occur seemed like a small
issue - not much energy at the ref freq for some applications. Our
synthesizers were of such requirements that there was a very tight balance
between lock time and spurious. The loop filtering took much care to get
the lock time and keep reference spurs down.

Regardless of the loop filter type, those are always fussy to avoid
pickup contamination of the VCO control line. But, knowing the
control voltage characteristics (delta-V v. frequency) over a range,
the design is strictly textbook formula stuff. It helps greatly if the
VCO control characteristics are linear versus frequency AND the
division ratio maximum to minimum number is as small as
possible.

I've seen a few applications where both the control voltage
characteristics were very non-linear AND the division ratio of the
PLL greater than 2:1 with the end result being an almost
impossible lock at the extreme ends of the tuning range. One
case was alleviated by extra circuitry from the division control to
generate a DC bias summed with the control voltage. Not too
swift since it took more parts, but better than failure.

In my own case, the filtering and shielding around the PFD to
VCO had to be rather severe in order to keep it stable (too
much high-energy circuitry rather nearby). Once that was
achieved, there was no wandering at a 1 KHz reference input
with proper values of known control voltage constants and
accurate calculation of loop filter values. It was "tight."

Len Anderson

In article , "Steve Nosko"
writes:

"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

Len - Avery, whomever,
Our experiences differ. When designing PLL synths back then for two-war
radio, we always saw the dead zone.

"Two-war radio?" PRC-25? Term not understood. Experience has
hands-on with everything from a PRC-8 to a PRC-104, but little with
the PRC-25 or -77.

In a type 2 loop (hope I'm remembering
my control theory correctly) the extra integration allows the VCO to float
around within the dead zone, causing a low freq rumble at times. You could
watch the phase wandering around on a scope on the two PD inputs.

If the loop is set for something like a 10 to 50 mSec lock-in time,
one has to look quick to see the actual lock-in. If the loop is
designed properly (VCO control voltage gain, time relative to the
reference frequency), there should not be any "wander."

In order to see the settling time from a large step-function of
frequency change, you need to sync a scope from the step
source and watch the jump-and-settle of the control voltage like
a damped sinewave. That's a quick check of loop control
action. Storage scope (old way) or digital scope (muy better)
are the best way to view that.

We would
force some small leakage current just to hold it up against one side of the
dead zone. Perhaps the types of requirements causes the difference. We
were in the audio range with the PD reference freq and lock times in the
tens of ms. if I recall correctly.

Most of the older PLLs had reference frequencies of 1 to 5 KHz.
That's a period of 1.0 mS to 200 uS. Without about 5 to 10
cycles for settling-in (to near invisibility), that would be about
10 to 2 mS, rather quick.

If I recall, the Fairchild chip did a better job of matching the delays.
The small overlap causing a narrow pulse to occur seemed like a small
issue - not much energy at the ref freq for some applications. Our
synthesizers were of such requirements that there was a very tight balance
between lock time and spurious. The loop filtering took much care to get
the lock time and keep reference spurs down.

Regardless of the loop filter type, those are always fussy to avoid
pickup contamination of the VCO control line. But, knowing the
control voltage characteristics (delta-V v. frequency) over a range,
the design is strictly textbook formula stuff. It helps greatly if the
VCO control characteristics are linear versus frequency AND the
division ratio maximum to minimum number is as small as
possible.

I've seen a few applications where both the control voltage
characteristics were very non-linear AND the division ratio of the
PLL greater than 2:1 with the end result being an almost
impossible lock at the extreme ends of the tuning range. One
case was alleviated by extra circuitry from the division control to
generate a DC bias summed with the control voltage. Not too
swift since it took more parts, but better than failure.

In my own case, the filtering and shielding around the PFD to
VCO had to be rather severe in order to keep it stable (too
much high-energy circuitry rather nearby). Once that was
achieved, there was no wandering at a 1 KHz reference input
with proper values of known control voltage constants and
accurate calculation of loop filter values. It was "tight."

Len Anderson

Dead-zone = phase noise. Very little dead-zone = very little phase noise.
Bigger dead-zone = bigger phase noise.
You can interpolate the rest for yourself.

Joe
W3JDR


"Avery Fineman" wrote in message
...
In article B_Htc.4677$pt3.1214@attbi_s03, "Rick Karlquist N6RK"
writes:

There are various fixes for the dead zone problem.
In the mid-1970's, Fairchild (the original company)
sold an "11C44" phase detector that got rid of the
dead zone by injecting a narrow pulse so that the
phase detector pulses would never have to try to
go to zero width. Eric Breeze holds the patent
on this technique; if interested read his patent.
Analog Devices makes that AD9901 phase detector
which gets around the dead zone by first dividing
the frequency by 2. However, it is not suitable
for a frequency synthesizer because of the large
spurious sidebands resulting from this technique.
Motorola had some patents on the circuits in its
MC145159 that dealt with the dead zone and sampling
sidebands. It also used a divide by 2 technique, that
was not documented; (we figured it out by observing
the chip's output). That chip may have been inherited by
On Semiconductor. It was originally developed for
some division of GE.

The "dead zone problem" is less a problem and more a
state of mind. :-)

When implemented with a charge-pump circuit (voltage
& time converter to current) between the PFD and loop
filter, it rather disappears into the woodwork of the whole
PLL. The phase difference between signal and reference
is proportional to the control voltage of the VCO producing
the basic frequency. There is ALWAYS going to be a
signal versus reference phase offset when the entire loop is
in lock so this dreaded "dead zone problem" will only show
up in a very narrow range of controlled frequency.

General intuitive thought on any PLL or other synthesizer
closed loop is that the relative phase between signal and
reference is zero. It isn't. If it was, then the VCO could not
be controlled. As a very rough indicator of VCO frequency,
that signal v. reference offset phase exists for quick scope
checking...when the control voltage range of the VCO is
known. Good for a quick bench check.

In practical terms, that dreaded "dead zone" isn't visible in a
real-world example.

Case in point: 23+ years ago, Rocketdyne Division of
Rockwell International (now a Division of Boeing) was beginning
work on a Deformable Mirror for laser work (they had a sizeable
optics group) that used a 1 MHz signal out of optics to indicate
the light phase error of an optical interferometer. I rigged up a
74H family phase-frequency detector circuit as the heart of that,
an integrator out of that into an A-to-D converter to get a digital
version for computer data manipulation. By all the careful
measurement, the expected dead zone didn't show up on any
graphing and the standard lab time interval counters could
resolve, accurately, 2 nanoseconds using time averaging.
[translates to rather less than a degree of phase error] The
optical physicists had been hopping up and down about "dead
zone" in meetings but the actual circuit performance didn't show it.

One reason for the non-observation of any dead zone is that the
digital gates forming the PFD were so lightly loaded in other-gate
capacitance that their propagation delays all tended to be the
same. Datasheet values of propagation delay of gates are all given
as maximums, rather worst-case things with lots of pFds connected
to outputs, etc. Put on half a prototype board, loaded only by other
gates of the PFD and the resistor input of an op-amp integrator, the
capacitance loading was minimal. [project was successful, and
spawned more work on deformable mirrors]

It can be an interesting academic problem to achieve a zero dead-
dead zone effect in a PFD, but thats about it. When working at
the comparison frequency of less than a few MHz, the PFD dead
zone due to differential propagation delays of the gates disappears
into the woodwork when using 74LS or faster digital families.

There's plenty to be concerned about in any frequency synthesizer
subsystem, but a phase-frequency detector gate structure is a
very minor problem in my opinion.

DDS and fractional-N loops in synthesizers have their own problems
such as spurious output, but those problems can't really be traced
to any PFD dead-zone effect. A PFD is wonderful as a control loop
element in that it can control a VCO (of the loop) from way off the
frequency and bring it into a lock phase range...from either worst-
case start-up frequency. [way back in the beginning of radio time,
lock loops had to use sawtooth sweep circuits to cure that start-up
condition, and couldn't control beyond +/- 90 degrees of phase
shift...PFDs easily handle +/-180 degrees]

Len Anderson
retired (from regular hours) electronic engineer person

In article , "W3JDR"
writes:

Dead-zone = phase noise. Very little dead-zone = very little phase noise.
Bigger dead-zone = bigger phase noise.
You can interpolate the rest for yourself.

I have to disagree with some of that.

First of all, a "dead zone" or the almost-exactly-in-phase condition,
occurs at only one VCO frequency where the control voltage sets
up the frequency for that in-phase condition.

Yes, at that exact frequency, there COULD be some phase noise.
But, the phase noise may NOT be from this "dead zone" effect.
Phase noise can come from MANY different sources. If it occurs
well away from the in-same-phase "dead zone" then the phase
noise is NOT caused by any "dead zone."

The relative phase between signal and reference inputs to a PFD
correspond to the VCO control voltage (times the charge-pump or
integrator circuit constants). Signal and reference phases when
in lock will always be offset from one another, one leading and one
lagging. A good loop will show a constant offset of phases even
when both inputs hold a constant phase.

Len Anderson

Let me try again to explain dead zone.

Many PLL's never experience the dead zone because the loop
filter is constructed using op amps with high (10 mV)
offset voltage specs. This offset forces the loop to
lock up outside the dead zone. If you use a low offset op amp,
and then put in an offset adjust pot to take out any
residual offset from the phase detector, you can observe
the spurious sidebands at the phase detection frequency
null out. However, you will then find that the loop bandwidth
has changed substantially, because you are in the dead zone
region. The VCO will get more phase noise because the
loop wanders around (like a bang-bang loop) in the dead
zone, and/or the change in loop bandwidth has de-optimized
the suppression of VCO noise by the PLL. I have
personally observed this and other engineers I have
mentored have also observed it (after first arguing with
me that it wouldn't happen). By the way, the pot
tweaking to null sidebands doesn't hold over temperature
(no surprise) so it's still bogus even without the dead zone
issue.

To correct previous misinformation about the 11C44: the
gates are not better matched; rather there is an extra pulse
injection circuit as described in Eric Breeze's patent. This
information is from a conversion with Eric Breeze 28 years
ago. The 11C44 hasn't been available for many years but
that was due to mismanagement of Fairchild (which
was bought by National) rather than lack of merit of
the 11C44. (There was a lot of great technology at
Fairchild screwed up by mismanagement).

Rick N6RK





"Avery Fineman" wrote in message
...
In article , "W3JDR"

writes:

Dead-zone = phase noise. Very little dead-zone = very little phase noise.
Bigger dead-zone = bigger phase noise.
You can interpolate the rest for yourself.

I have to disagree with some of that.

First of all, a "dead zone" or the almost-exactly-in-phase condition,
occurs at only one VCO frequency where the control voltage sets
up the frequency for that in-phase condition.

Yes, at that exact frequency, there COULD be some phase noise.
But, the phase noise may NOT be from this "dead zone" effect.
Phase noise can come from MANY different sources. If it occurs
well away from the in-same-phase "dead zone" then the phase
noise is NOT caused by any "dead zone."

The relative phase between signal and reference inputs to a PFD
correspond to the VCO control voltage (times the charge-pump or
integrator circuit constants). Signal and reference phases when
in lock will always be offset from one another, one leading and one
lagging. A good loop will show a constant offset of phases even
when both inputs hold a constant phase.

Len Anderson

In article bWTtc.11435$eY2.451@attbi_s02, "Rick Karlquist N6RK"
writes:

Let me try again to explain dead zone.

Many PLL's never experience the dead zone because the loop
filter is constructed using op amps with high (10 mV)
offset voltage specs. This offset forces the loop to
lock up outside the dead zone.

With any phase-frequency detector, the width of the output
rectangular wave (from the digital portion) is proportional
to the control voltage output. That width can be converted
to a DC control voltage by a charge pump (pins 4, 5, 10, 11
in either the MC4044 or 11C44 package) or done externally
in an integrator such as with an op-amp.

When locked, the signal and reference inputs of the PFD will
be in-phase but the relative phases are offset in time. It is
that offset which eventually produces the control voltage that
brings the VCO into the in-phase condition.

A "dead zone" does indeed exist in all such circuits but it
will take effect ONLY in the VCO frequency region where the
phases of signal and reference input are the same or very
nearly the same. At any other VCO frequency the "dead zone"
has no effect since the phase offsets of signal and reference
are away from that "dead zone." Note: The signal and reference
phases will be "in-phase" meaning that they are both on the
same frequency but the signal is offset in phase from the
reference.

The "offset" of any extra circuit elements to an op-amp used
in coupling the PFD to the VCO can be used as a stop-gap
cure for the "dead-zone" but that still is effective only in the
phase relationship of the signal v. reference inputs where they
are nearly the same phase.

If you use a low offset op amp,
and then put in an offset adjust pot to take out any
residual offset from the phase detector, you can observe
the spurious sidebands at the phase detection frequency
null out.

Observation shows the entirety of the loop action. It does
not pin down a cause of the spurious outputs. Those spurious
outputs can be caused by a number of different things.

However, you will then find that the loop bandwidth
has changed substantially, because you are in the dead zone
region. The VCO will get more phase noise because the
loop wanders around (like a bang-bang loop) in the dead
zone, and/or the change in loop bandwidth has de-optimized
the suppression of VCO noise by the PLL.

The VCO control voltage curve sets part of the loop filter's
frequency response and is called the "gain" of the loop
feedback. Bandwidth is dependent primarily by the
reference frequency plus the lock-in response time desired.
Too much "gain" and the whole loop goes into oscillation,
never settling down; too little and the loop takes a very long
time to lock in (and may never do so). Curvature of the slope
of the PFD output (converted from time to voltage) affects the
"gain" and thus the total closed-loop condition.

I have
personally observed this and other engineers I have
mentored have also observed it (after first arguing with
me that it wouldn't happen).

The "dead zone" does indeed exist but I'm simply saying that
(1). It isn't an ogre ready to strike fear in use; (2). It doesn't
effect a PLL lock over all VCO frequencies...just that narrow
range of VCO frequencies where the relative phase offsets of
the signal and reference inputs to the PFD are about the same.

The original question involved a six 2-input, two 3-input, and
(one 4-input) gate EQUIVALENT of the '44. That original '44
design is an elegant one, a sort of gigantic flip-flop on steroids
which will work over a +/-180 degree range. It is far superior to
the old types of phase detectors which had only a +/- 90 degree
operating range. The time characteristics (or phase relationship
of input rectangular signals) of such a circuit can be much
improved by using faster-responding digital logic families. By
using 74F or 74H or other very fast gates, the "dead zone" can
be made very small, enough to essentially forget about any such
effects on the overall PLL with a 10 KHz or lower reference
frequency.

If there is anxiety over the PFD operation, it can be examined
with a 'scope and a stable, delayed signal pulse synced from
the reference input. The '44 circuit type doesn't need square
waves but can operate solely on leading edges. With a time-
interval-averaging counter, the signal input phase can be set/
characterized very accurately as well as the output pulse width.
Lacking a time counter, a 'scope (hopefully with delayed time
base function) can be used for coarser measurement. The
'scope will display the "dead zone" condition.

To correct previous misinformation about the 11C44: the
gates are not better matched; rather there is an extra pulse
injection circuit as described in Eric Breeze's patent.

That's not included in the diagram shown on the 11C44 data
sheet website you referenced. That gate diagram and charge
pump and Darlington bipolar circuits are exactly as in the
original Motorola '44 data sheet. Either PFD gate arrangement
can be duplicated using "discrete" logic gates.

In my opinion there's an elegant simplicity of the '44 gate
arrangement which adequately fulfills its purpose of not only
operating over a +/- 180 degree input phase offset but also
staying on extremes of low or high frequency signal input
condition, ideal for PLL start-up. I'd like to know the original
circuit designer to send thanks for such elegance in circuitry.

Other manufacturers (such as RCA and Intersil) have duplicated
the '44 PFD gate arrangement with success. It can be copied
with ordinary logic gates without problem. If there is a region of
a PLL to concentrate on, I'd say it is in the pulse width to DC
control voltage following circuit and the loop filter (and its
shielding and isolation).

Len Anderson
retired (from regular hours) electronic engineer person