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Input stage for VHF frequency counter in an FPGA?

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February 23rd 06, 01:06 PM posted to sci.electronics.design,comp.arch.fpga,rec.radio.amateur.homebrew

Jan Panteltje

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Input stage for VHF frequency counter in an FPGA?

On a sunny day (22 Feb 2006 19:01:44 -0800) it happened
wrote in .com:

The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Just a partial reply... I think 7400 series should stop way below 200mHz,
perhaps 50MHz?

I would make a small diff amplifier, did something 40 years ago (yes 40!)
with I think it was BFY90 transistors, then invert with 2 more and drive
the LVDS input.

-------------------------------- +5 or + 12
| | |
[ ] [ ] [ ] R4
| |------------ __|__
|-----|-------- | | |
|/ \| | | |/e \|
---| NPN |---- | |----| |---
in |\ e / |bias2 | |\ PNP /| |
|___| | | | |
| ---------|-----|----
| / | |
---| |---- |----------- LVDS +
bias | \ | |----------- LVDS -
| | |
[ ] [ ] [ ]
| | R5 | R6
---------------------------------------------- GND

R4 could be a current source too, set it so it is guaranteed that
the voltage across R5 and R6 (max i in one leg) cannot exceed FPGA
max in.

Gives you some input protection
The 'bias voltages can be generated with diode drop.
No time now to enter it in spice to get response.....
You can use simple junction FETS for the first stage too.

There are also nice chips, but transistors I have always in the box.

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