Hi,
If I have a few TTL chips on the same PCB as all my PLL's (see previous
threads). Would it be a good idea to put a little choke in the supply line
up against each TTL chip, with cap decoupling either side?

What about 100uH and 2 100nF?

Will that reduce any noise problems I have?

Thanks,
John.

I don't believe chokes should be necessary. Good 0.1 or 0.01 at each
package should be enough. Parallel bypass caps is not a good idea because
the larger one will go inductive above its self resonant freq and resonate
with the other creating a parallel resonant, high impedance "non-bypass".


HOWEVER...

Make sure your ground paths are isolated from each other. The digital chip
ground path should have nothing in common with the VCO and Phase Det
grounds. The VCO is extremely sensitive to any voltage variations between
ground and its supply and if you have ground variations and a good supply,
it is just like power supply ripple.
All the digital grounds should go directly back to the supple input to
the board and the analog grounds the same and this must be two completely
isolated paths.

Sometimes *cutting* ground paths around a VCO improves spurs.


GOOD:

VCO GND -----------------------\
\
-Supply GND
/
/
TTL GND -----------------------


BAD:

VCO GND --\ This run *HAS* impedance and
\ voltage drop in the form of pulses.
----------------------Supply GND
/ And there fore modulates the VCO.
/
TTL GND --


73, Steve, K9DCI


"John Wilkinson" wrote in message
.. .
Hi,
If I have a few TTL chips on the same PCB as all my PLL's (see previous
threads). Would it be a good idea to put a little choke in the supply line
up against each TTL chip, with cap decoupling either side?

What about 100uH and 2 100nF?

Will that reduce any noise problems I have?

Thanks,
John.

Steve Nosko wrote:

I don't believe chokes should be necessary. Good 0.1 or 0.01 at each
package should be enough. Parallel bypass caps is not a good idea because
the larger one will go inductive above its self resonant freq and resonate
with the other creating a parallel resonant, high impedance "non-bypass".


HOWEVER...

Make sure your ground paths are isolated from each other. The digital
chip ground path should have nothing in common with the VCO and Phase Det
grounds. The VCO is extremely sensitive to any voltage variations between
ground and its supply and if you have ground variations and a good supply,
it is just like power supply ripple.
All the digital grounds should go directly back to the supple input to
the board and the analog grounds the same and this must be two completely
isolated paths.

Sometimes *cutting* ground paths around a VCO improves spurs.


GOOD:

VCO GND -----------------------\
\
-Supply GND
/
/
TTL GND -----------------------


BAD:

VCO GND --\ This run *HAS* impedance and
\ voltage drop in the form of pulses.
----------------------Supply GND
/ And there fore modulates the VCO.
/
TTL GND --


73, Steve, K9DCI


"John Wilkinson" wrote in message
.. .
Hi,
If I have a few TTL chips on the same PCB as all my PLL's (see previous
threads). Would it be a good idea to put a little choke in the supply
line up against each TTL chip, with cap decoupling either side?

What about 100uH and 2 100nF?

Will that reduce any noise problems I have?

Thanks,
John.

There are two schools of thought on RF grounding of mixed analogue and
digital circuits. I have always had good results with a single, complete
ground *plane* for all of the analogue and digital circuitry, and separate
supplies with their own regulators near the loads (or at least their own
decoupling), for the noisy blocks and the sensitive blocks. Others may say
that what I do doesn't work for them, but it has worked for me.

Chris

I agree with Chris on this one. I'd add some things, though. Because
of transmission-line effects, the ground return currents for digital
ICs will tend to flow on the ground plane in the region very near the
supply lines, so keep the supply lines for the digital section away
from the sensitive analog section.

Another way to make the digital stuff quiet is to realize that a great
deal of the high frequency currents involved with digital are in the
I/O lines that go into, and especially go out of, chips. It helps to
pay special attention to all digital signal lines. You can soften the
edges by putting small series resistors physically very near each
output, so as to limit the current into the capacitance of the trace
and inputs it goes to. It can help a lot, too, to use differential
signalling even when you don't need to. Just as differential lines in
the sensitive analog input end help to reject noise, so differential
lines radiate less than single ended ones. Differential outputs also
make for quieter power supply lines, since one output turns on whenever
another turns off, maintaining constant supply current. Fully
differential ECL is particularly quiet on the power supplies, but
likely not worth the effort because of how power-hungry it is and how
little integration you can get on a single chip.

We do use little ferrites on power supply lines; they provide effective
high frequency isolation. 0.1uF bypasses aren't really very good at
bypassing 100MHz -- it's nice to also use some smaller values, and to
use physically small parts that have low parasitic inductance. It pays
to THINK about the layout quite a bit, and understand what you are
doing and why.

For sensitive analog circuitry that draws constant current, there's a
cute and very effective power supply cleaning circuit and ap note on
the Wenzel Associates website. The noise out of a typical linear
regulator will significantly add to the phase noise of a PLL. That
site also has some good info about low phase noise circuits. (somewhat
aside: Wenzel makes some really fine low-noise oscillators, and
Charles Wenzel is a very nice, and very interesting, guy.)

I think this all says that what Chris does also DOES work for me, and I
can affirm that much of it is in a commercial environment where we are
achieving cutting-edge performance.

Cheers,
Tom

I borrowed 5V from the USB line of a data acquisition card -- it is somewhat
noisy so I put a 100uH choke and a small tantalum on the line -- it works.

You can get excellent noise performance (far exceeding the Wetzel modified
LM317 circuit) with Linear Technologies LT1763 and LT1964 ultra-low noise
regulators -- they will do 100mA on their own and can be used to drive a
pass transistor if you need more juice. Unfortunately, post regulating any
digital supply for analog circuitry burns up watts.

fwiw -- while dual bypass caps aren't a good idea for digital circuits
(because of the ringing aforementioned) -- in analog they are recommended
for certain low noise apps because of susceptibility to EMI and RFI.

Huh? The LT1763 claims 20uVRMS noise in a 100kHz bandwidth. That's
about 63nV/rtHz. The data sheets shows it MUCH worse at low
frequencies, and the LT1964 a bit worse yet. I'm not sure who Wetzel
is, but the (modified) Wenzel circuit I've used has given me noise down
in the very few nanovolts/rtHz region down to 10Hz and below, depending
on just how I implement it. Perhaps we're thinking of different
circuits for cleaning supplies. The one I'm thinking of is very useful
even with "quiet" regulators like the LT parts. Easy implementations
get you 20dB improvement in noise, and careful design and parts
specification can get you 40dB, with noise as low as a couple nV/rtHz
and a 1/f corner well below 100Hz, by using an op amp like the AD797
and low noise precision resistors in what is essentially a bridge
circuit to cancel the regulator noise.

Guess the jury is still out on the multiple bypass cap values, too.
Xilinx and TI at least both recommend -- strongly recommend -- multiple
values. Yes, you want to avoid resonances, but I've had much less
trouble with bypass caps in parallel than with chokes resonating with
with bypass caps. Now that's something to look out for! The trick
with parallel bypass caps is to insure that the Q of any parasitic
inductances is low.

Cheers,
Tom