OK, I think I got it.

Let's say I want Vdd = 8V. Say I have an RF chock in the Drain then Vds
is almost 8V.

Say I want 5mA bias current.

I look at the Vds vs Id and find that VG1-s = -0.2V for this condition.
(So actual VDs is 7.8V)

Next I use a source resistor of VG1-s/ Id = 40 Ohms
As VG1 = VG1-s + VG1 - IDxRS the Gate voltage applied is 0V.

The graph on the datasheet mentions that this is the output when VG2-s
is 4V.

So now I calculate VG2 = VG2-s + ID x RS = 4.2V

I suppose that I can make Rs smaller to the point where VG1-s is 0V on
the graph.(Occurs at 10mA for BF998).

If I want higher Q point I then add positive bias to V1. I also
understand I can get around 10dB attenuation by lowering VG2-s from 4.2V
towards 0V but need to make it negative if I want to switch the signal
off altogether (If I was to use the FET as say a ASK or OOK modulator).

Thanks



tim gorman wrote:
David wrote:


Hi,

Pretty fundamental I know but can someone please explain the steps for
setting up bias for a Dual Gate MOSFET.

I know I could place a pot on the gate and source for each circuit and
play with values but I would like a method that enables me to calculate
the values.

The main issue is how to determine values for Rs and Gate 2 Voltage.

I am using BF998 and want to have a "play" at 5V and 8V supply.

The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2
But Idss is stated as 2-18mA
Vp Gate 1 is given as a range from 1-2V
Vp gate 2 is given as range from 0.5 to 1.5V

If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at
the source to determine Vgs ?

Any help much appreciated.

Regards

David


One way of doing this is to get the datasheet for the FET you are using.
There should be a graph that shows the operating characteristic curves. The
x-axis will be Vds and the Y-axis will be the drain current Id. The
characteristic curves will be for various levels of Vgs. Pick an operating
point based on the type of amplifier you want. Let's suppose it will be
Class A. Assume the FET has a power supply voltage of 40v and an Idss of
10ma. Let's say that you pick a point in the middle of the operating curves
that gives an Id of 6ma and a Vds of 20v in order to get the maximum swing
out of the amplifer. Looking at the characteristic curves shows that this
will require a Vgs of about -1v. Now you have everything you need.

If Vgs needs to be -1v and Id is 6ma (assume Id and Is will be the same) you
need a resistor of Vd/Id (R = V/I) or about 166 ohms.

The gate resistor you see in FET amps is not really there for biasing but
more to set the input impedance of the amplifier. As long as the leakage
current from the gate to the source is small, Vgs is set by the bias
resistor in the source lead.

tim ab0wr

FWIW, I found the following SPICE model for the BF998 on the web -- note
that the two MOSFETs VMAX are dissimilar, a lot of the entries are for
parasitic elements:

* BF998 SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS
* ENVELOPE SOT143
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
..SUBCKT BF998 1 2 3 4
L10 1 10 0.12N
L20 2 20 0.12N
L30 3 30 0.12N
L40 4 40 0.12N
L11 10 11 1.20N
L21 20 21 1.20N
L31 30 31 1.20N
L41 40 41 1.20N
C13 10 30 0.085P
C14 10 40 0.085P
C21 10 20 0.017P
C23 20 30 0.085P
C24 20 40 0.005P
D11 42 11 ZENER
D12 42 41 ZENER
D21 32 11 ZENER
D22 32 31 ZENER
RS 10 12 100
MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6


..MODEL ZENER D BV=10 CJO=1.2E-12 RS=10


..MODEL GATE1
+ NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9
+ NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.1E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12


..MODEL GATE2
+ NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9
+ NSUB=3E15 VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.1E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12


..ENDS BF998

Ah, but that's a model for just one BF998. The one you pull out of the
drawer might bear very little resemblance to it.

Roy Lewallen, W7EL

jack wrote:
FWIW, I found the following SPICE model for the BF998 on the web -- note
that the two MOSFETs VMAX are dissimilar, a lot of the entries are for
parasitic elements:
. . .

Doesn't say much about their quality control if the devices are that
dissimilar.

FWIW, I have developed a semiconductor and tube curve tracer for use within
Multisim -- create the component in Multisim, plug it into the curve tracer,
run the test and compare with the manufacturer's charts.

I have also built a tube curve tracer -- same will apply for
semiconductors -- even published an article on it. With this i can compare
the characteristics of the device vis a vis mfr data sheet AND the
simulation in EWB.

Jack

"Roy Lewallen" wrote in message
...
Ah, but that's a model for just one BF998. The one you pull out of the
drawer might bear very little resemblance to it.

Roy Lewallen, W7EL

jack wrote:
FWIW, I found the following SPICE model for the BF998 on the web -- note
that the two MOSFETs VMAX are dissimilar, a lot of the entries are for
parasitic elements:
. . .

In ancient times I set up a VHF amplifier test circuit with a dual-gate
3NXXX and measured gain and IM distortion vs bias parameters, DC feedback
and negative RF feedback. I was able to compare many samples and found that
I could get adequate (for my purposes) uniformity for a dozen samples in a
particular application. The tradeoff is reduced gain to get "improved"
uniformity. Trying to get max results from a single stage is not as good as
two or three cascaded more modest stages. The cost of this approach is of
course not minimal. The first stage dominates total noise figure.

Bill W0IYH

"David" wrote in message
...
OK, I think I got it.

Let's say I want Vdd = 8V. Say I have an RF chock in the Drain then Vds is
almost 8V.

Say I want 5mA bias current.

I look at the Vds vs Id and find that VG1-s = -0.2V for this condition.
(So actual VDs is 7.8V)

Next I use a source resistor of VG1-s/ Id = 40 Ohms
As VG1 = VG1-s + VG1 - IDxRS the Gate voltage applied is 0V.

The graph on the datasheet mentions that this is the output when VG2-s is
4V.

So now I calculate VG2 = VG2-s + ID x RS = 4.2V

I suppose that I can make Rs smaller to the point where VG1-s is 0V on the
graph.(Occurs at 10mA for BF998).

If I want higher Q point I then add positive bias to V1. I also understand
I can get around 10dB attenuation by lowering VG2-s from 4.2V
towards 0V but need to make it negative if I want to switch the signal off
altogether (If I was to use the FET as say a ASK or OOK modulator).

Thanks



tim gorman wrote:
David wrote:


Hi,

Pretty fundamental I know but can someone please explain the steps for
setting up bias for a Dual Gate MOSFET.

I know I could place a pot on the gate and source for each circuit and
play with values but I would like a method that enables me to calculate
the values.

The main issue is how to determine values for Rs and Gate 2 Voltage.

I am using BF998 and want to have a "play" at 5V and 8V supply.

The formulae for Id is Id = Idss(1-Vgs/Vp) ^ 2
But Idss is stated as 2-18mA
Vp Gate 1 is given as a range from 1-2V
Vp gate 2 is given as range from 0.5 to 1.5V

If I apply say 4V to G1 and 0V to G2, how do I calculate the voltage at
the source to determine Vgs ?

Any help much appreciated.

Regards

David


One way of doing this is to get the datasheet for the FET you are using.
There should be a graph that shows the operating characteristic curves.
The
x-axis will be Vds and the Y-axis will be the drain current Id. The
characteristic curves will be for various levels of Vgs. Pick an
operating
point based on the type of amplifier you want. Let's suppose it will be
Class A. Assume the FET has a power supply voltage of 40v and an Idss of
10ma. Let's say that you pick a point in the middle of the operating
curves
that gives an Id of 6ma and a Vds of 20v in order to get the maximum
swing
out of the amplifer. Looking at the characteristic curves shows that this
will require a Vgs of about -1v. Now you have everything you need. If Vgs
needs to be -1v and Id is 6ma (assume Id and Is will be the same) you
need a resistor of Vd/Id (R = V/I) or about 166 ohms. The gate resistor
you see in FET amps is not really there for biasing but
more to set the input impedance of the amplifier. As long as the leakage
current from the gate to the source is small, Vgs is set by the bias
resistor in the source lead.

tim ab0wr