I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W) wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.

Both of the above may provide acceptable jitter.

3. a no-VCO approach - frequency double twice using XOR gates, then divide by
five and finally by two in say a 7490. Simple glue logic chips.

4. use a micro.

I would certainly expect both 3 & 4 to present more jitter than well-implemented
VCO solutions. If jitter is critical to the application, this needs to be
indicated.

"budgie" wrote in message
...
On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W)
wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all
provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg
source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.


I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap
to alter the VXO frequency (or use an ordinary diode or LED as the varicap,
see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent
stability of the VXO will allow you to use a very slow PLL, which will
result in minimal jitter.

Hans G0UPL
http://www.HansSummers.com

On Wed, 18 Feb 2004 13:07:48 -0000, "Hans Summers"
wrote:


"budgie" wrote in message
.. .
On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W)
wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all
provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg
source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.


I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap
to alter the VXO frequency (or use an ordinary diode or LED as the varicap,
see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent
stability of the VXO will allow you to use a very slow PLL, which will
result in minimal jitter.

Agreed, a VCXO is a good way to go if you do need a VCO.

Remember, the o/p didn't reference any jitter sensitivity in the task, which may
be simple timing or gated counting of a pulse train. Neither is
jitter-sensitive.

If jitter isn't an issue, I'd personally KISS and go with #3. Small footprint,
small dissipation, no tuned circuits, no PLL parameters to calculate, no VCO's
to build, no VCXO's or xtals to buy. Only one RC time constant to calculate (or
optimise by SOT) to minimise jitter if inclined to bother.

Thankyou everyone for your ideas.
I think I'll go with the VCXO phase locked to the 10Mhz reference.
Why did'nt I think of that ;-(
atb Mike W
--

Thankyou everyone for your ideas.
I think I'll go with the VCXO phase locked to the 10Mhz reference.
Why did'nt I think of that ;-(
atb Mike W
--

On Wed, 18 Feb 2004 13:07:48 -0000, "Hans Summers"
wrote:


"budgie" wrote in message
.. .
On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W)
wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all
provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg
source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.


I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap
to alter the VXO frequency (or use an ordinary diode or LED as the varicap,
see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent
stability of the VXO will allow you to use a very slow PLL, which will
result in minimal jitter.

Agreed, a VCXO is a good way to go if you do need a VCO.

Remember, the o/p didn't reference any jitter sensitivity in the task, which may
be simple timing or gated counting of a pulse train. Neither is
jitter-sensitive.

If jitter isn't an issue, I'd personally KISS and go with #3. Small footprint,
small dissipation, no tuned circuits, no PLL parameters to calculate, no VCO's
to build, no VCXO's or xtals to buy. Only one RC time constant to calculate (or
optimise by SOT) to minimise jitter if inclined to bother.

"budgie" wrote in message
...
On Wed, 18 Feb 2004 09:17:11 GMT, (Mike W)
wrote:

I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

Several approaches spring to mind. You stated "accurate" - they all
provide
that, but jitter is introduced in all of them:

1. VCO at 4MHz, divide by 4 and lock to Fref = 1MHz from your 10 Meg
source
divided by ten.

2. VCO at a multiple of 10M - say 40 MHz - locked to your 10M ref and
divided down (by in this case 10) to give 4 MHz output.


I would suggest using a 4MHz crystal oscillator as your VCO. Small varicap
to alter the VXO frequency (or use an ordinary diode or LED as the varicap,
see http://www.hanssummers.com/radio/varicap/varicap.htm). The inherent
stability of the VXO will allow you to use a very slow PLL, which will
result in minimal jitter.

Hans G0UPL
http://www.HansSummers.com

Take a look at Analog Devices' line of DDS chips. Pretty much a one-chip
(needs ucontroller to drive it) digital solution to turn your 10MHz clock
into virtually any frequency below 5 MHz (in theory; below 4MHz in easy
practicality). The AD9834 only consumes 20mw at 3.3 VDC. There are many
other devices in the product line. Many have built-in comparators to produce
square-wave output.

Joe
W3JDR


"Mike W" wrote in message
...
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw

"W3JDR" wrote in message
...
Take a look at Analog Devices' line of DDS chips. Pretty much a one-chip
(needs ucontroller to drive it) digital solution to turn your 10MHz clock
into virtually any frequency below 5 MHz (in theory; below 4MHz in easy
practicality). The AD9834 only consumes 20mw at 3.3 VDC. There are many
other devices in the product line. Many have built-in comparators to
produce
square-wave output.

Joe
W3JDR



Joe, I'd gladly use the Analog Devices DDS chips if they offered them in
something other than a SadoMasochistic Device (SMD) package. It's a darn
shame they can't make a limited run (say 10k) of some of these chips in a
PDIP package for hams and other r.f. experimenters.

If they put the AD9835 in a PDIP and sold it for about $10.00 (the TSSOP
packaged version sells for about $6, I think) , I'd buy a dozen for various
projects, but in the tiny SMD package they're nothing but useless to me.

I'm new to the newsgroup and am sure that this is not the first gripe about
SMD's, but I refuse to use them - not because I can't (at least not yet),
but because I don't want to endure the angst.
--
Chip
KC5UES
real E-mail Address:







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