rickman wrote in :

Before integration comes demodulation. How would you demodulate and
integrate in the analog domain on a 100 uW power budget? The signal is
PSK. But that is not the real reason. My goal is to show it is
possible to do this entirely in the digital domain.


Low Vf diode in feedback loop of op-amp? I'm curious though, it's an
interesting thought, doing it all in digital equipment, but why? The main
drive behind me 'off-shelf' remark is that I suspect the best answer already
exists in many forms. I'm curious about what makes a need to keep searching.
I'm not denying it, far from it, there's usually more than one good way to
do something, I'm just not sure what the differentiating factor is in this
case.

On 10/30/2014 1:02 PM, Lostgallifreyan wrote:
rickman wrote in :

Before integration comes demodulation. How would you demodulate and
integrate in the analog domain on a 100 uW power budget? The signal is
PSK. But that is not the real reason. My goal is to show it is
possible to do this entirely in the digital domain.


Low Vf diode in feedback loop of op-amp? I'm curious though, it's an
interesting thought, doing it all in digital equipment, but why? The main
drive behind me 'off-shelf' remark is that I suspect the best answer already
exists in many forms. I'm curious about what makes a need to keep searching.
I'm not denying it, far from it, there's usually more than one good way to
do something, I'm just not sure what the differentiating factor is in this
case.

I don't know about "best" but you can buy a time code receiver chip that
spits out a demodulated signal to be decoded by an MCU. At that point
the data rate is pretty low so an MCU can run at very low power levels,
likely dominated by the quiescent current.

When you suggest an op amp, we already covered that ground and they
aren't low power enough. I'm curious how they amplify the signal in the
receiver chip with the whole circuit drawing a very low power level.

--

Rick

On 10/30/2014 01:27 PM, rickman wrote:
On 10/30/2014 1:02 PM, Lostgallifreyan wrote:
rickman wrote in :

Before integration comes demodulation. How would you demodulate and
integrate in the analog domain on a 100 uW power budget? The signal is
PSK. But that is not the real reason. My goal is to show it is
possible to do this entirely in the digital domain.


Low Vf diode in feedback loop of op-amp? I'm curious though, it's an
interesting thought, doing it all in digital equipment, but why? The main
drive behind me 'off-shelf' remark is that I suspect the best answer already
exists in many forms. I'm curious about what makes a need to keep searching.
I'm not denying it, far from it, there's usually more than one good way to
do something, I'm just not sure what the differentiating factor is in this
case.

I don't know about "best" but you can buy a time code receiver chip that
spits out a demodulated signal to be decoded by an MCU. At that point
the data rate is pretty low so an MCU can run at very low power levels,
likely dominated by the quiescent current.

When you suggest an op amp, we already covered that ground and they aren't
low power enough. I'm curious how they amplify the signal in the receiver
chip with the whole circuit drawing a very low power level.

Motorola's app notes on the old 4000 series CMOS included
various analog circuits, including use of a CMOS inverter
as an amplifier. I'm enough of a packrat that I keep those
things.

4000 series may not be useful in your case, but the circuits
or variants of them may apply in newer CMOS implementations.

'Course calling it all digital may be just a game if your
input stage is a digital circuit biased to operate in an
analog mode.

George

George Cornelius wrote:
Motorola's app notes on the old 4000 series CMOS included
various analog circuits, including use of a CMOS inverter
as an amplifier. I'm enough of a packrat that I keep those
things.

I'm sure this guy (who is coming back on this subject regularly) is
not going to consider that low-power. The inverter was driven into
the area between switching to '1' and to '0' by using a feedback
resistor, and so both output fets are conducting and drawing current
from Vcc to Gnd.

On 11/3/2014 3:08 AM, Rob wrote:
George Cornelius wrote:
Motorola's app notes on the old 4000 series CMOS included
various analog circuits, including use of a CMOS inverter
as an amplifier. I'm enough of a packrat that I keep those
things.

I'm sure this guy (who is coming back on this subject regularly) is
not going to consider that low-power. The inverter was driven into
the area between switching to '1' and to '0' by using a feedback
resistor, and so both output fets are conducting and drawing current
from Vcc to Gnd.

If you I am "the guy", whether or not this is low power enough depends
on the power. My understanding is that when operated in the linear mode
significant current can flow in a CMOS device. So likely this isn't low
enough power, no.

I'm very curious about how they do it in the commercial chips. I have
seen block diagrams and they show an amplifier as the first part of the
chip. Maybe the design really isn't all that low power. Rather than
running at low power all the time, they just limit the duty cycle of the
receiver. "Atomic" clocks don't need to monitor the signal except for a
few minutes each day.

--

Rick

rickman wrote:
On 11/3/2014 3:08 AM, Rob wrote:
George Cornelius wrote:
Motorola's app notes on the old 4000 series CMOS included
various analog circuits, including use of a CMOS inverter
as an amplifier. I'm enough of a packrat that I keep those
things.

I'm sure this guy (who is coming back on this subject regularly) is
not going to consider that low-power. The inverter was driven into
the area between switching to '1' and to '0' by using a feedback
resistor, and so both output fets are conducting and drawing current
from Vcc to Gnd.

If you I am "the guy", whether or not this is low power enough depends
on the power. My understanding is that when operated in the linear mode
significant current can flow in a CMOS device. So likely this isn't low
enough power, no.

I'm very curious about how they do it in the commercial chips. I have
seen block diagrams and they show an amplifier as the first part of the
chip. Maybe the design really isn't all that low power. Rather than
running at low power all the time, they just limit the duty cycle of the
receiver. "Atomic" clocks don't need to monitor the signal except for a
few minutes each day.

I have several battery-powered "atomic clocks" and all of them enable
the receiver only for a few minutes, either every hour or twice a day
depending on the particular design. The receiver I have connected to
my computer is of course enabled all the time.

Many years ago I worked on a "shop-shelf tag" system that used a low
frequency receiver in a single-chip design, and it also had a power
saving mechanism. The tags (powered by single lithium cell like those
used as a BIOS backup battery) were usually in a sleep mode only driving
the LCD, and once every so many seconds they briefly enabled the receiver.
To run an update, the controller sent a wakeup signal that lasted long
enough to get the attention of all tags, then it sent the updates
addressed to each tag, and finally an end-of-transmission signal that
put everything back into sleep mode. The lithium cell lasted several
years, I think.