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Old February 25th 06, 05:11 AM posted to sci.electronics.design,comp.arch.fpga,rec.radio.amateur.homebrew
 
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Default Input stage for VHF frequency counter in an FPGA?

wrote:
Fred Bloggs wrote:
... but what
would make sense today?


http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

That sounds like a good idea, because theoretically we actually have
some on hand somewhere, I'll have to see if I can scare them up.


Found one and wired it up as the datasheet suggests - cap coupled input
to half the differential pair, the other side floating at the reference
output pin voltage with decoupling cap to ground, terminating resistor
across the pair. Worked quite well.

The xilinx S3 kit from digilent doesn't seem to be designed with using
the differential input capability as the pairs are split up all over
the place. Not certain that I couldn't bias one input of a pair as a
reference wherever it is and drive the other pin wherever that is, but
putting it all in a little package seemed simpler.



 
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