wrote:
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
or a little more if it's high-Z. The output of the device under test
has a transformer and then a series cap to create an unbalanced output.


I did something ugly with a 3.3v cmos 7406 varient and a feedback
resistor, which works well enough to get an accurate reading on one
version of the device under test, but not on the other (both have been
verified with real test equipment) It also tends to self-oscillate
with no input...

I'm surprised any CMOS 7406 variant really goes to 200MHz! I think you
got lucky with the one that did work.

What would be the right way to do this using on hand parts, such as
abused logic, little 1:1 or 2:1 RF transformers, etc?

I like high-speed comparators (often called "differential receivers" or
"LVDS receivers" on the spec sheet) for this.

One idea is to
use another gate with a feedback resistor and cap to ground in the hope
of establishing the threshold level, and then using a transformer to
swing another input above and below this. Most parts on hand are SMD -
which means dead bug construction in SOIC scale under the maginifier -
discourages extensive experimentation.

The nice thing about differential receivers a

1. Easy to set the comparison level.
2. Lowish input impedance but not too low, such that you set the
impedance by putting a 50 or 100 or whatever ohm resistor there.
3. At least for the non-LVDS parts, there's only one or two receivers
per package so even when it's not SMD it's easy to do dead-bug
prototyping.
4. They already have some semblance of defined open-circuit response
(usually called "fail-safe" for some bizarre reason in the spec sheets)
to prevent oscillating.

Why do most abuse-of-logic RF applications seem to use NAND gates
rather than inverters? From a digital perspective NAND gates are a
universal element, but once you tie their inputs together, is there
something to be gained from having two inputs in parallel?

Usually the hex inverter packages cost a little bit more than the
4xNAND gate packages. It's nice to have the extra input to act as an
enable etc. And once you start running these parts into the linear
region you probably do not really trust using the other sections for
other functions.

Is there a way to use a differential input configuration on an FPGA to
input a balanced RF signal directly? Theoretically this should be an
FPGA clock input... The device in use currently is an Altera Stratix
II, but a Xilinx S3 kit is available.

You can even feed in non-balanced RF subject to some limitations.

If ordering things, what would be a good default low supply voltage
HF/VHF gain component to have on hand? I seem to recall lots of
last-millenium ham designs using the MC1350P video IF amp, but what
would make sense today?

VHF? MMIC's, at least as long as you have only need for AC coupling.

Tim.

From: on Wed, Feb 22 2006 7:01 pm

The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
or a little more if it's high-Z. The output of the device under test
has a transformer and then a series cap to create an unbalanced output.

snip

If you want some good results, use a high-speed comparator
device. The Maxim MAX9010 family of comparators is fast
(5 nSec propagation delay) and it works into a TTL load.

At 1 V p-p you've got the input overdrive to insure fast
rise and fall times of the output. Note: 200 MHz (if that
is really what you wanted to write) has a period of 5 nSec
so even this very fast comparator is going to be pushed for
a good output. On the other hand it is STABLE and won't
"go into oscillation with no input."

http://www.maxim-ic.com

Samples are available. One in the family is in a SOT23
package, the rest smaller.


If ordering things, what would be a good default low supply voltage
HF/VHF gain component to have on hand? I seem to recall lots of
last-millenium ham designs using the MC1350P video IF amp, but what
would make sense today?

The MC1350P is second-sourced by Lansdale. It is still a very
good differential in/out building block with good AGC control.
The MC1349P is a pin/function equivalent and can be ordered from
Dieter Gentzow's PartsAndKits.com at 3 for $3. Same place is a
good source of small-quantity toroidal cores. Both ICs are
called out with 12 VDC supplies but they will work down to
9 VDC with little degredation. Open-collector outputs, constant
5 KOhm || 5 pFd input, AGC control down to 60 db (if needed).

wrote:

Jan Panteltje wrote:

Just a partial reply... I think 7400 series should stop way below 200mHz,
perhaps 50MHz?

It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't
tell) and it's self oscillating at 294 mhz - (it's stable enough for
the counter to read... a fast scope shows it approximately as a
sinewave.

It seems to be oscillating at about 1/tpd... can't even really pull it
much with finger capacitance - only about 10 mhz.

Interestingly, if I short a the floating input-output pair of an unused
inverter with the scope probe, that runs a bit slower around 260 mhz...
wheras the gate in use has about 20k of resistance in the feedback
path.

I would make a small diff amplifier, did something 40 years ago (yes 40!)
with I think it was BFY90 transistors, then invert with 2 more and drive
the LVDS input.

I may give your transistor circuit a try, either with components or
simulation, thanks.

There are some newer low voltage CMOS gates that are much faster than AC
series, I think they are called LVC and a few other names depending on the
manufacturer. The really fast ones don't support 5V supply operation
because they are made on a fine geometry process. This also makes them
faster. It would be very hard to stop it from self oscillating with no
input signal. In order to have a meaningful way of determining if you have
satisfied this requirement for not self-oscillating, you would first have
to define what is the minimum input amplitude that you expect it to be able
to accept and produce an output with reasonable duty cycle etc. Another
approach would be to make an input buffer that does self oscillate and make
a separate detector that measures the input signal amplitude and disables
the measurement when the input amplitude is below a certain threshold.

Chris

Chris

Fred Bloggs wrote:
... but what
would make sense today?


http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

That sounds like a good idea, because theoretically we actually have
some on hand somewhere, I'll have to see if I can scare them up.

While connecting to the FPGA directly would be simpler, I do like the
idea of using an external chip as a bit of a 'fuse'. (Though
transformer coupling into the FPGA should reduce some risk)

On Thu, 23 Feb 2006 16:23:13 +1300, Jim Granville
wrote:

wrote:
The other day I found myself needing a short gate time ~200 mhz
frequency counter for an automated test, and since I had an FPGA board
on hand I whipped one up quickly. Getting it reading and reporting to
my computer was the easy part.

Ah, the input stage....

Does the FPGA have LVDS option inputs ?
If it is new enough to have those, they are differential
amplifiers, designed for current mode signals, and will work
with thresholds 1V.
IIRC the LVDS spec has +100mV and -100mV levels.
Normally, they need a common mode bias of just over 1V, and the
better ones will also tolerate rail-rail drive (on ONE ip),
but at reduced speed specs.
-jg

Second that. We've tested the Xilinx Spartan3 LVDS inputs and they are
excellent, super-fast comparators.

John

wrote:
Fred Bloggs wrote:
... but what
would make sense today?


http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

That sounds like a good idea, because theoretically we actually have
some on hand somewhere, I'll have to see if I can scare them up.

Found one and wired it up as the datasheet suggests - cap coupled input
to half the differential pair, the other side floating at the reference
output pin voltage with decoupling cap to ground, terminating resistor
across the pair. Worked quite well.

The xilinx S3 kit from digilent doesn't seem to be designed with using
the differential input capability as the pairs are split up all over
the place. Not certain that I couldn't bias one input of a pair as a
reference wherever it is and drive the other pin wherever that is, but
putting it all in a little package seemed simpler.

http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

Be sure to check the output with a scope.

Years ago, I used a PECL=TTL part. That was real/old, 5V TTL.
The problem was that I really wanted a CMOS output and what I
got was a TTL signal that only went up to 4V or so. We had to
run it through an AC dead-bug to get what we wanted.

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Hal Murray wrote:
http://www.onsemi.com/PowerSolutions...=MC100EPT21DR2

Be sure to check the output with a scope.

Years ago, I used a PECL=TTL part. That was real/old, 5V TTL.
The problem was that I really wanted a CMOS output and what I
got was a TTL signal that only went up to 4V or so. We had to
run it through an AC dead-bug to get what we wanted.

Good point to keep in mind. In this case though it's all 3.3v
families, and LVTTL seems to have nearly the same Vih/Vil spec as
LVCMOS. The part is spec'd with minimum Voh of 2.4v.