Multiply by four, then divide by five and by two. Or divide by five,
then multiply by four and divide by two. For the best symmetry, you
should expect to use a divide-by-two in the last stage, though you can
get close to 50% with triggering off both rising and falling edges.
There are other possible trick ways but the mpy/div are
straightforward. You could, for example, divide the ref by five and a
4MHz VCO by two and build a PLL to control the 4MHz VCO.

Cheers,
Tom

(Mike W) wrote in message ...
I have a need to produce an accurate 4Mhz 50% dutycycle TTL squarewave
to use as a timebase.

I have a 10Mhz IQD frequency standard of suitable accuracy. How can I
divide this to produce the 50% duty cycle 4Mhz signal?. Is it even
possible with logic alone?. I can see how to mix with either 6Mhz or
14Mhz, but this then detracts from the required accuracy.

atb Mikw